XC1800 Datasheet, PDF (8/16 Pages) Xilinx, Inc – XC1800 Series of In-System

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XC1800 Series of In-System Programmable Configuration PROMs
Controlling Configuration PROMs
Connecting the FPGA device with the configuration PROM.
• The DATA output(s) of the of the PROM(s) drives the
DIN input of the lead FPGA device.
• The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s).
• The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
• The OE/RESET input of all PROMs is best driven by
the INIT output of the lead FPGA device. This
connection assures that the PROM address counter is
reset before the start of any (re)configuration, even
when a reconfiguration is initiated by a V_CC glitch.
• The PROM CE input can be driven from either the LDC
or DONE pins. Using LDC avoids potential contention
on the DIN pin. If the CE input of the first (or only)
PROM can be driven by the DONE output of the first
FPGA device, provided that DONE is not permanently
grounded. Otherwise, LDC can be used to drive CE, but
must then be unconditionally High during user
operation. CE can also be permanently tied Low, but
this keeps the DATA output active and causes an
unnecessary supply current of 10 mA maximum.
• Express mode is similar to slave serial mode. The
DATA is clocked out of the SPROM one byte per CCLK
instead of one bit per CCLK cycle. To synchronize with
the FPGA the first byte of data is valid 20ns before the
second rising edge of CCLK and then on every
consecutive CCLK thereafter. Note: When
programming in Express mode, to accommodate the
4us set-up time on the INIT pin of the Spartan FPGA,
the first line of the configuration stream must not be
placed higher than the 3C byte address of the PROM.
Initiating FPGA Configuration
The XC1800 devices incorporate a pin named CF that is
controllable through the JTAG CONFIG instruction. Execut-
ing the CONFIG instruction through JTAG will pulse the CF
low for 300-500ns, which will reset the FPGA and initiate
configuration.
The CF pin must be connected to the PROGRAM pin on
the FPGA to use this feature.
Selecting Configuration Modes
The XC1800 accommodates serial and parallel methods of
configuration. The configuration modes are selectable
through a user control register in the XC1800 device. This
control register is accessible through JTAG, using the Xilinx
JTAG Programmer software.
FPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block
(CLB) and their associated interconnections are estab-
lished by a configuration program. The program is loaded
either automatically upon power up, or on command,
depending on the state of the three FPGA mode pins. In
Master Serial mode, the FPGA automatically loads the con-
figuration program from an external memory. Xilinx PROMs
are designed for compatibility with the Master Serial mode.
Upon power-up or reconfiguration, an FPGA enters the
Master Serial mode whenever all three of the FPGA mode-
select pins are Low (M0=0, M1=0, M2=0). Data is read from
the PROM sequentially on a single data line. Synchroniza-
tion is provided by the rising edge of the temporary signal
CCLK, which is generated during configuration.
Master Serial Mode provides a simple configuration inter-
face. Only a serial data line and two control lines are
required to configure an FPGA. Data from the PROM is
read sequentially, accessed via the internal address and bit
counters which are incremented on every valid rising edge
of CCLK. If the user-programmable, dual-function DIN pin
on the FPGA is used only for configuration, it must still be
held at a defined level during normal operation. The Xilinx
FPGA families take care of this automatically with an on-
chip default pull-up resistor.
Programming the FPGA With Counters
Unchanged Upon Completion
When multiple FPGA-configurations for a single FPGA are
stored in a PROM, the OE/RESETpin should be tied Low.
Upon power-up, the internal address counters are reset
and configuration begins with the first program stored in
memory. Since the OE/RESETpin is held Low, the address
counters are left unchanged after configuration is com-
plete. Therefore, to reprogram the FPGA with another pro-
gram, the DONE line is pulled Low and configuration
begins at the last value of the address counters.
This method fails if a user applies OE/RESET during the
FPGA configuration process. The FPGA aborts the config-
uration and then restarts a new configuration, as intended,
but the PROM does not reset its address counter, since it
never saw a High level on its OE input. The new configura-
tion, therefore, reads the remaining data in the PROM and
interprets it as preamble, length count etc. Since the FPGA
is the master, it issues the necessary number of CCLK
pulses, up to 16 million (2²⁴) and DONE goes High. How-
ever, the FPGA configuration will be completely wrong, with
potential contentions inside the FPGA and on its output
pins. This method must, therefore, never be used when
there is any chance of external reset during configuration.
Cascading Configuration PROMs
For multiple FPGAs configured as a daisy-chain, or for
FPGAs requiring larger configuration memories, cascaded
PROMs provide additional memory. Multiple XC1800
devices can be concatenated by using the CEO output to
drive the CE input of the following device. The clock inputs
and the data outputs of all XC1800 devices in the chain are
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September 17, 1999 (Version 1.3)