XC1800 Datasheet, PDF (6/16 Pages) Xilinx, Inc – XC1800 Series of In-System

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XC1800 Series of In-System Programmable Configuration PROMs
IEEE 1149.1 Boundary-Scan (JTAG)
The XC1800 family is fully compliant with the IEEE Std.
1149.1 Boundary-Scan, also known as JTAG. A Test
Access Port (TAP) and registers are provided to support all
required boundary scan instructions, as well as many of the
optional instructions specified by IEEE Std. 1149.1. In addi-
tion, the JTAG interface is used to implement in-system
programming (ISP) to facilitate configuration, erasure, and
verification operations on the XC1800 device.
Table 3 lists the required and optional boundary-scan
instructions supported in the XC1800. Refer to the IEEE
Std. 1149.1 specification for a complete description of
boundary-scan architecture and the required and optional
instructions.
Table 3: Boundary Scan Instructions
Boundary- Binary Code
Description
Scan
(7:0)
Command
Required Instructions
BYPASS 11111111 Enables BYPASS
SAMPLE/ 00000001 Enables boundary-scan
PRELOAD
SAMPLE/PRELOAD
operation
EXTEST
00000000 Enables boundary-scan
EXTEXT operation
Optional Instructions
CLAMP
11111010 Enables boundary-scan
CLAMP operation
HIGHZ
11111100 3-states all outputs
simultaneously
IDCODE
11111110 Enables shifting out 32-
bit IDCODE
USERCODE 11111101 Enables shifting out 32-
bit USERCODE
XC1800 Specific Instructions
CONFIG
11101110 Initiates FPGA
configuration by pulsing
CF pin low
Instruction Register
The Instruction Register (IR) for the XC1800 is 8-bits wide
and is connected between TDI and TDO during an instruc-
tion scan sequence. In preparation for an instruction scan
sequence, the instruction register is parallel loaded with a
fixed instruction capture pattern. This pattern is shifted out
onto TDO (LSB first), while an instruction is shifted into the
instruction register from TDI. The detailed composition of
the instruction capture pattern is illustrated in Figure 3.
The ISP Status field, IR(4), contains logic 1 if the device is
currently in ISP mode; otherwise, it will contain 0. The
Security field, IR(3), will contain logic 1 if the device has
been programmed with the security option turned on; other-
wise, it will contain 0.
IR(7:5) IR(4) IR(3) IR(2) IR(1:0)
ISP
TDI-> 0 0 0 _Status Security 0
0 1 ->TDO
Note: IR(1:0) = 01 is specified by IEEE Std. 1149.1
Figure 3: Instruction Register values loaded into IR
as part of an instruction scan sequence
Boundary Scan Register
The boundary-scan register is used to control and observe
the state of the device pins during the EXTEST, SAMPLE/
PRELOAD, and CLAMP instructions. Each output pin on
the XC1800 has two register stages that contribute to the
boundary-scan register, while each input pin only has one
register stage.
For each output pin, the register stage nearest to TDI con-
trols and observes the output state, and the second stage
closest to TDO controls and observes the 3-state enable
state of the pin.
For each input pin, the register stage controls and observes
the input state of the pin.
Identification Registers
The IDCODE is a fixed, vendor-assigned value that is used
to electrically identify the manufacturer and type of the
device being addressed. The IDCODE register is 32-bits
wide. The IDCODE register can be shifted out for examina-
tion by using the IDCODE instruction.
The IDCODE register has the following binary format:
vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1
where
v= the die version number
f=the family code (50h for XC1800 family)
a=the ISP PROM product ID (06h for the XC1804)
c=the company code (49h for Xilinx)
Note: The LSB of the IDCODE register is always read as
logic 1 as defined by IEEE Std. 1149.1
Table 4: IDCODES Assigned to XC1800 devices
ISP-PROM
XC1801
XC1804
IDCODE
05004093h
05006093h
Table 4 lists the IDCODE register values for the XC1800
devices.
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September 17, 1999 (Version 1.3)