XC1800 Datasheet, PDF (11/16 Pages) Xilinx, Inc – XC1800 Series of In-System

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XC1800 Series of In-System Programmable Configuration PROMs
5V Tolerant I/Os
The I/Os on each re-programmable PROM are fully 5V tol-
erant even through the core power supply is 3.3 volts. This
allows 5V CMOS signals to connect directly to the PROM
inputs without damage. In addition, the 3.3V V_CC power
supply can be applied before or after 5V signals are applied
to the I/Os. In mixed 5V/3.3V/2.5V systems, the user pins,
the core power supply (V_CC), and the output power supply
(V_CCO) may have power applied in any order. This makes
the PROM devices immune to power supply sequencing
issues.
Reset Activation
On power up, OE/RESET is held low until the XC1800 is
active (1ms) and able to supply data after receiving a CCLK
Table 6: Truth Table for PROM Control Inputs
pulse from the FPGA. OE/RESET is connected to an exter-
nal resistor to pull OE/RESET HIGH releasing the FPGA
INIT and allowing configuration to begin. OE/RESET is
held low until the XC1800 voltage reaches the operating
voltage range. If the power drops below 2.0 Volts, the
PROM will reset.
Standby Mode
The PROM enters a low-power standby mode whenever
CE is asserted High. The output remains in a high imped-
ance state regardless of the state of the OE input. JTAG
pins TMS, TDI and TDO can be 3-state or high.
Control Inputs
OE/RESET
CE
Internal Address
DATA
Low
High
Low
Low
Low
High
if address < TC: increment
if address > TC: don’t change
Held reset
Held reset
active
3-state
3-state
3-state
High
High
Held reset
3-state
Note: TC = Terminal Count = highest address value. TC+1 = address 0.
Outputs
CEO
High
Low
High
High
High
I_cc
active
reduced
active
standby
standby
September 17, 1999 (Version 1.3)
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