XC1800 Datasheet, PDF (3/16 Pages) Xilinx, Inc – XC1800 Series of In-System

R
XC1800 Series of In-System Programmable Configuration PROMs
Pin
Name
Boundary
Scan
Order
Function
Pin Description
44-pin
VQFP
44-pin
PLCC
20-pin
SOIC & PLCC
CEO
13
DATA OUT Chip Enable (CEO) output is connected
21
27
13
14
OUTPUT
ENABLE
to the CE input of the next PROM in the
chain. This output is Low when the CE
and OE/RESET inputs are active AND
the internal address counter has been in-
cremented beyond its Terminal Count
(TC) value. When the PROM has been
read, CEO will follow CE as long as OE/
RESET is High. When OE/RESET goes
Low, CEO stays High until the PROM is
brought out of reset by bringing OE/RE-
SET High. CEO can be programmed to
be either active High or active Low.
GND
GND is the ground connection.
6, 18, 28 & 3, 12, 24 &
11
41
34
TMS
MODE The state of TMS on the rising edge of
5
11
5
SELECT TCK determines the state transitions at
the Test Access Port (TAP) controller.
TMS has an internal 50K ohm resistive
pull-up on it to provide a logic 1 to the de-
vice if the pin is not driven.
TCK
CLOCK This pin is the JTAG test clock. It se-
7
13
6
quences the TAP controller and all the
JTAG test and programming electronics.
TDI
DATA IN This pin is the serial input to all JTAG in-
3
9
4
struction and data registers. TDI has an
internal 50K ohm resistive pull-up on it to
provide a logic 1 to the system if the pin is
not driven.
TDO
DATA OUT This pin is the serial output for all JTAG
31
37
17
instruction and data registers. TDO has
an internal 50k ohm resistive pull-up on it
to provide a logic 1 to the system if the pin
is not driven.
V_CC
Positive voltage supply of 3.3V for inter- 17, 35 & 38 23, 41 & 44
18 & 20
nal logic and input buffers.
V_CCO
Positive voltage supply connected to the 8, 16, 26 & 14, 22, 32 &
19
output voltage drivers.
36
42
*Programmable for Serial Mode only on 18512 and 1801.
September 17, 1999 (Version 1.3)
3