XC1800 Datasheet, PDF (10/16 Pages) Xilinx, Inc – XC1800 Series of In-System

R
XC1800 Series of In-System Programmable Configuration PROMs
Vcc
DOUT
FPGA
MODES
OPTIONAL
Daisy-chained
FPGAs with
Different
Configurations
OPTIONAL
Slave FPGAs
with Identical
Configurations
Vcc Vcco
DIN
CCLK
DONE
INIT
PROGRAM
VCC VCCO
DATA
CLK _FIRST
CE ^PROM CEO
OE/RESET
CF
(Low Resets the Address Pointer)
Master Serial Mode
DATA
CLK ^Cascaded
PROM
CE
OE/RESET
3.3V
M0
CS
M1
WRITE
M2 _VIRTEX
Select MAP
NC BUSY
DONE
CCLK
PROGRAM D0-D7
INIT
I/O*
I/O*
4.7k
4.7k
8
Vcc Vcco
External Osc
3.3V
4.7K
VCC VCCO
XC18xx
CLK
D0-D7
CE
OE/RESET
CEO
CF
Virtex Select MAP Mode
Vcc ^Vcco
Vcc
4k
VCC VCCO
CEO
D0-D7 ⁸
XC18xx
CE
CF
OE/RESET
CLK
Vcc
M0
CS1
M1
DOUT
Spartan XL
D0-D7
PROGRAM DONE
INIT
CCLK
CCLK
Spartan XL Express Mode
M0 M1
CS1
DOUT
Optional
Daisy-Chained
Spartan XL
D0-D7
PROGRAM DONE
INIT
CCLK
To Additional
Optional
Daisy-Chained
Devices
To Additional
Optional
Daisy-Chained
Devices
*CS and WRITE must be pulled down to be used as I/O. One option is shown.
Figure 5: (a) Master Serial Mode (b) Virtex Select MAP Mode (c) Spartan XL Express Mode
10
September 17, 1999 (Version 1.3)