XC1800 Datasheet, PDF (2/16 Pages) Xilinx, Inc – XC1800 Series of In-System

XC1800 Series of In-System Programmable Configuration PROMs
Pinout and Pin Description
Table 1: Pin Names and Descriptions
Pin
Name
Boundary
Scan
Order
Function
Pin Description
D0
4
DATA OUT D0 is the DATA output pin to provide data
3
OUTPUT ^{for configuring an FPGA in serial mode.}
ENABLE
D1
6
DATA OUT D0- D7 are the output pins to provide par-
5
OUTPUT
ENABLE
allel data for configuring a Xilinx FPGA in
express mode.
D2
2
DATA OUT
1
OUTPUT
ENABLE
D3
8
DATA OUT
7
OUTPUT
ENABLE
D4
24
DATA OUT
23
OUTPUT
ENABLE
D5
10
DATA OUT
9
OUTPUT
ENABLE
D6
17
DATA OUT
16
OUTPUT
ENABLE
D7
14
DATA OUT
13
OUTPUT
ENABLE
CLK
0
DATA IN
Each rising edge on the CLK input incre-
ments the internal address counter if both
CE is low and OE/RESET is high.
20
OE/
19
RESET
18
DATA IN When Low, this input holds the address
DATA OUT
counter reset and the DATA output at
high impedance.
OUTPUT
ENABLE
CE
15
DATA IN When CE is High, this pin puts the device
into standby mode. The DATA output pin
is at High impedance, and the device is in
low power standby mode.
CF
22
DATA OUT Allows JTAG CONFIG instruction to ini-
21
DATA IN
tiate FPGA configuration without power-
ing down FPGA.
44-pin
VQFP
40
29
42
27
9
25
14
19
43
13
15
10
R
44-pin
PLCC
2
20-pin
SOIC & PLCC
1
35
16
4
2
33
15
15
7*
31
14
20
9
25
12
5
3
19
8
21
10
16
7*
2
September 17, 1999 (Version 1.3)