WM8962B Datasheet, PDF (64/295 Pages) Wolfson Microelectronics plc – Ultra-Low Power Stereo CODEC with Audio Enhancement DSP, 1W Stereo Class D Speaker Drivers and Ground Referenced Headphone Drivers

WM8962
DMICCLK pin
MIC1 output
(Left Channel)
MIC2 output
(Right Channel)
hi-Z
1
1
1
2
2
2
DMICDAT
(Left/Right channels
interleaved)
121212
Figure 22 Digital Microphone Interface Timing
The digital microphone interface control fields are described in Table 22. Note that the ADC and
Record Path filters must be enabled and the sample rate must be set in order to ensure correct
operation of all DSP functions associated with the digital microphone. Volume control for the Digital
Microphone Interface signals is provided using the ADC Volume Control.
See “Analogue To Digital Converter (ADC)” for details of the ADC Enable and ADC digital volume
control functions. See “General Purpose Input/Output (GPIO)” for details of configuring the DMICCLK
and DMICDAT functions. See “Clocking and Sample Rates” for details of the sample rate control.
REGISTER
ADDRESS
R25 (19h)
Pwr Mgmt (1)
BIT
LABEL
10 DMIC_ENA
DEFAULT
0
3 ADCL_ENA
0
2 ADCR_ENA
0
Table 22 Digital Microphone Interface Control
DESCRIPTION
Enables Digital Microphone mode.
0 = Audio DSP input is from ADC
1 = Audio DSP input is from digital
microphone interface
Note that, when the digital
microphone interface is selected,
the ADCL_ENA and ADCR_ENA
registers must also be set to enable
the left and right digital microphone
channels respectively.
Left ADC Enable
0 = Disabled
1 = Enabled
Right ADC Enable
0 = Disabled
1 = Enabled
Note that, in addition to setting the DMIC_ENA bit as described in Table 22, the pins GPIO2, GPIO3,
GPIO5 or GPIO6 must also be configured to provide the digital microphone interface function. See
“General Purpose Input/Output (GPIO)” for details.
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Rev 4.3