WM8962B Datasheet, PDF (245/295 Pages) Wolfson Microelectronics plc – Ultra-Low Power Stereo CODEC with Audio Enhancement DSP, 1W Stereo Class D Speaker Drivers and Ground Referenced Headphone Drivers

REGISTER BIT
ADDRESS
R143 (8Fh) 7:0
PLL 16
Register 8Fh PLL 16
LABEL
DEFAULT
DESCRIPTION
PLL3_K [7:0]
1001_0111 Fractional Multiply for PLL3
(MSB = 0.5)
This is bits 7:0 of a 24-bit field
WM8962
REGISTER BIT
ADDRESS
R150 (96h)
1
PLL DLL
0
Register 96h PLL DLL
LABEL
SEQ_ENA
Reserved
DEFAULT
DESCRIPTION
1
PLL Control Sequencer Enable
0 = Disabled
1 = Enabled
This bit must be set to 0 when MCLK is selected as the PLL
Clock Source.
1
Reserved - do not change
REGISTER
ADDRESS
R155 (9Bh)
FLL Control
(1)
BIT
LABEL
DEFAULT
DESCRIPTION
6:5 FLL_REFCLK_S
00
FLL Clock Source
RC [1:0]
00 = MCLK
01 = BCLK
10 = Internal oscillator
11 = Reserved
3
Reserved
1
Reserved - do not change
2
FLL_FRAC
1
FLL Fractional Mode enable
0 = Integer Mode
1 = Fractional Mode
1 FLL_OSC_ENA
0
FLL_ENA
Register 9Bh FLL Control (1)
Fractional Mode (FLL_FRAC=1) is recommended in all
cases
0
FLL Oscillator enable
0 = Disabled
1 = Enabled
(Note that this field is required for free-running FLL modes
only)
0
FLL Enable
0 = Disabled
1 = Enabled
Rev 4.3
245