WM8962B Datasheet, PDF (247/295 Pages) Wolfson Microelectronics plc – Ultra-Low Power Stereo CODEC with Audio Enhancement DSP, 1W Stereo Class D Speaker Drivers and Ground Referenced Headphone Drivers

WM8962
REGISTER BIT
ADDRESS
R160 (A0h) 15:0
FLL Control
(6)
LABEL
FLL_THETA
[15:0]
Register A0h FLL Control (6)
DEFAULT
DESCRIPTION
0000_0000
_0001_100
0
FLL Fractional multiply for FREF.
Only valid when FLL_FRAC = 1.
This field sets the numerator (multiply) part of the
FLL_THETA / FLL_LAMBDA ratio. It is coded as LSB = 1.
REGISTER BIT
ADDRESS
LABEL
R161 (A1h)
FLL Control
(7)
15:0
FLL_LAMBDA
[15:0]
Register A1h FLL Control (7)
DEFAULT
DESCRIPTION
0000_0000
_0111_110
1
FLL Fractional multiply for FREF.
Only valid when FLL_FRAC = 1.
This field sets the denominator (dividing) part of the
FLL_THETA / FLL_LAMBDA ratio. It is coded as LSB = 1.
Note that it is required that FLL_LAMBDA > 0 in all cases
(Integer and Fractional modes).
REGISTER BIT
ADDRESS
R162 (A2h) 9:0
FLL Control
(8)
LABEL
FLL_N [9:0]
Register A2h FLL Control (8)
DEFAULT
DESCRIPTION
00_0000_1 FLL Integer multiply for FREF
000
(LSB = 1)
REGISTER BIT
ADDRESS
R252 (FCh)
2
General test
0
1
LABEL
Reserved
AUTO_INC
Register FCh General test 1
DEFAULT
DESCRIPTION
1
Reserved - do not change
1
Enables address auto-increment
(applies to 2-wire I2C mode only)
0 = Disabled
1 = Enabled
REGISTER BIT
ADDRESS
R256 (0100h) 2
DF1
1
0
Register 0100h DF1
LABEL
DEFAULT
DESCRIPTION
DF1_SHARED_
0
DF1 Shared Coefficients Enable
COEFF
0 = Disabled
1 = Enabled
DF1_SHARED_
0
DF1 Shared Coefficients Select
COEFF_SEL
0 = Both channels use left coefficients
1 = Both channels use right coefficients
DF1_ENA
0
DF1 Enable in ADC path
0 = Disabled
1 = Enabled
Rev 4.3
247