WM8962B Datasheet, PDF (154/295 Pages) Wolfson Microelectronics plc – Ultra-Low Power Stereo CODEC with Audio Enhancement DSP, 1W Stereo Class D Speaker Drivers and Ground Referenced Headphone Drivers

WM8962
DSP, ADC, DAC CLOCK CONTROL
The clocking of the DSP is derived from MCLK. The clocking of the ADC and DAC circuits is derived
from SYSCLK. The associated dividers are configured automatically by the WM8962.
The DSP clocking rate is controlled by DSPCLK_DIV. In automatic clocking mode, this is configured
automatically by the WM8962 to ensure DSPCLK <= 24.576MHz. (Note that the DSPCLK_DIV divider
is a read-only register; it cannot be written to.)
The ADC clocking rate is controlled by ADCSYS_CLK_DIV. In automatic clocking mode, the WM8962
uses this divider to derive the most suitable SYSCLK / fs ratio, where fs is the ADC sampling rate.
The DAC clocking rate is controlled by DACSYS_CLK_DIV. In automatic clocking mode, the WM8962
uses this divider to derive the most suitable SYSCLK / fs ratio, where fs is the DAC sampling rate.
REGISTER
ADDRESS
R4 (04h)
Clocking 1
BIT
10:9
LABEL
DSPCLK_DIV
[1:0]
8:6
ADCSYS_CLK_
DIV [2:0]
5:3
DACSYS_CLK_
DIV [2:0]
Table 100 DSP, ADC, DAC Clock Control
DEFAULT
DESCRIPTION
00
DSP Clock Divider
00 = MCLK
01 = MCLK / 2
10 = MCLK / 4
11 = Reserved
This field is for read-back only; it is set
automatically and cannot be adjusted.
000
ADC Sample Rate Divider
000 = SYSCLK
001 = Reserved
010 = SYSCLK / 2
011 = SYSCLK / 3
100 = SYSCLK / 4
101 = Reserved
110 = SYSCLK / 6
111= Reserved
This field is for read-back only; it is set
automatically and cannot be adjusted.
100
DAC Sample Rate Divider
000 = SYSCLK
001 = Reserved
010 = SYSCLK / 2
011 = SYSCLK / 3
100 = SYSCLK / 4
101 = Reserved
110 = SYSCLK / 6
111= Reserved
This field is for read-back only; it is set
automatically and cannot be adjusted.
154
Rev 4.3