WM8962B Datasheet, PDF (146/295 Pages) Wolfson Microelectronics plc – Ultra-Low Power Stereo CODEC with Audio Enhancement DSP, 1W Stereo Class D Speaker Drivers and Ground Referenced Headphone Drivers

WM8962
REGISTER
ADDRESS
R7 (07h)
Audio
Interface 0
R8 (08h)
Clocking2
BIT
LABEL
6 MSTR
3:0 BCLK_DIV
R14 (0Eh)
Audio
Interface 2
10:0 AIF_RATE
[10:0]
DEFAULT
DESCRIPTION
0
0100
040h
Audio Interface Mode Select
0 = Slave mode
1 = Master mode
BCLK Rate
0000 = DSPCLK
0001 = Reserved
0010 = DSPCLK / 2
0011 = DSPCLK / 3
0100 = DSPCLK / 4 (default)
0101 = Reserved
0110 = DSPCLK / 6
0111 = DSPCLK / 8
1000 = Reserved
1001 = DSPCLK / 12
1010 = DSPCLK / 16
1011 = DSPCLK / 24
1100 = Reserved
1101 = DSPCLK / 32
1110 = DSPCLK / 32
1111 = DSPCLK / 32
LRCLK Rate
LRCLK clock output =
BCLK / AIF_RATE
Integer (LSB = 1)
Valid from 4..2047
Table 92 Digital Audio Interface Clock Control
Default (040h) = 64 BCLKs per LRCLK
COMPANDING
The WM8962 supports A-law and -law companding on both transmit (ADC) and receive (DAC) sides
as shown in Table 93.
REGISTER
ADDRESS
R9 (09h)
Audio
Interface 1
BIT
LABEL
4 DAC_COMP
3 DAC_COMPMODE
2 ADC_COMP
1 ADC_COMPMODE
Table 93 Companding Control
DEFAULT
DESCRIPTION
0
DAC Companding Enable
0 = disabled
1 = enabled
0
DAC Companding Type
0 = µ-law
1 = A-law
0
ADC Companding Enable
0 = disabled
1 = enabled
0
ADC Companding Type
0 = µ-law
1 = A-law
146
Rev 4.3