WM8962B Datasheet, PDF (184/295 Pages) Wolfson Microelectronics plc – Ultra-Low Power Stereo CODEC with Audio Enhancement DSP, 1W Stereo Class D Speaker Drivers and Ground Referenced Headphone Drivers

WM8962
CONTROL INTERFACE
The WM8962 is controlled by writing to its control registers. Readback is available for all registers.
The Control Interface can operate as either a 2-, 3- or 4-wire interface:
 2-wire (I2C) mode uses pins SCLK and SDA
 3-wire (SPI) mode uses pins C¯¯S/GPIO6, SCLK and SDA
 4-wire (SPI) mode uses the C¯¯S /GPIO6, SCLK and SDA pins; the SDOUT function is
provided on a GPIO pin
Readback is provided on the bi-directional pin SDA in 2-/3-wire modes. In 4-wire mode, the SDOUT
readback function must be enabled on one of the GPIO pins - see “General Purpose Input/Output
(GPIO)”.
In 3-wire and 4-wire SPI modes, the C¯¯S function is provided using the C¯¯S/GPIO6 pin. In these control
interface modes, GPIO6 must be configured as C¯¯S by setting GP6_FN = 00h and GP6_DIR = 1. Note
that this is the default setting of GPIO6.
The WM8962 uses 16-bit register addresses and 16-bit data in 2-wire (I2C) mode; the WM8962 uses
15-bit register addresses in 3-wire and 4-wire (SPI) modes.
The configuration parameters in registers R16896 (4200h) to R21139 (5293h) are 24-bit words,
arranged within the 16-bit register address space. Each 24-bit word must be written to the register
map in full, MSBs first, before attempting to read back the value. Failure to do this may give incorrect
read/write behaviour.
When updating the configuration parameters for any DSP feature(s), it is recommended to write all of
the associated registers, in incremental address order, before reading back any values.
Note that the Control Interface function can be supported with or without system clocking. Where
possible, the register map access is synchronised with SYSCLK in order to ensure predictable
operation of cross-domain functions. See “Clocking and Sample Rates” for further details of Control
Interface clocking.
SELECTION OF CONTROL INTERFACE MODE
The WM8962 Control Interface Mode is determined by the logic level on the CIFMODE pin, as shown
in Table 121.
CIFMODE
INTERFACE FORMAT
Low
2 wire (I2C) Mode
High
3- or 4- wire (SPI) Modes
Table 121 Control Interface Mode Selection
184
In 2-wire (I2C) Control Interface mode, Auto-Increment mode may be selected. This enables multiple
write and multiple read operations to be scheduled faster than is possible with single register
operations, and is illustrated in Figure 67, Figure 68 and Figure 69. The auto-increment option is
enabled when the AUTO_INC register bit is set. This bit is defined in Table 122. Auto-increment is
enabled by default.
In SPI modes, 3-wire or 4-wire operation may be selected using the SPI_4WIRE register bit.
In SPI modes, the Continuous Read mode may be selected using the SPI_CONTRD bit. This enables
multiple register read operations to be scheduled faster than is possible with single register
operations. When SPI_CONTRD is set, the WM8962 will readback from incremental register
addresses as long as C¯¯S is held low and SCLK is toggled.
In 3-wire (SPI) mode, register readback is provided using the bi-directional pin SDA. During data
output, the SDA pin can be configured as CMOS or Open Drain, using the SPI_CFG register bit.
In 4-wire (SPI) mode, register readback is provided using SDOUT, which must be configured on one
of the GPIO pins.
When GPIO5 is configured as SDOUT, it may be configured as CMOS or as ‘Wired OR’ using the
SPI_CFG bit. In CMOS mode, SDOUT is driven low when not outputting register data. In ‘Wired OR’
mode, SDOUT is un-driven (high impedance) when not outputting register data bits. Note that the
Rev 4.3