WM8962B Datasheet, PDF (190/295 Pages) Wolfson Microelectronics plc – Ultra-Low Power Stereo CODEC with Audio Enhancement DSP, 1W Stereo Class D Speaker Drivers and Ground Referenced Headphone Drivers

WM8962
CONTROL WRITE SEQUENCER
The Control Write Sequencer is a programmable unit that forms part of the WM8962 control interface
logic. It provides the ability to perform a sequence of register write operations with the minimum of
demands on the host processor - the sequence may be initiated by a single operation from the host
processor and then left to execute independently.
Default sequences for Start-Up of each output driver and Shut-Down are provided (see “Default
Sequences” section). It is recommended that these default sequences are used unless changes
become necessary.
When a sequence is initiated, the sequencer performs a series of pre-defined register writes. The host
processor informs the sequencer of the start index of the required sequence within the sequencer’s
memory. At each step of the sequence, the contents of the selected register fields are read from the
sequencer’s memory and copied into the WM8962 control registers. This continues sequentially
through the sequencer’s memory until an “End of Sequence” bit is encountered; at this point, the
sequencer stops and an Interrupt status flag is asserted. For cases where the timing of the write
sequence is important, a programmable delay can be set for specific steps within the sequence.
Note that the Control Write Sequencer’s internal clock is derived from the internal clock SYSCLK
which must be enabled as described in “Clocking and Sample Rates”. The clock division from
SYSCLK is handled transparently by the WM8962 without user intervention, provided that SYSCLK is
configured as specified in “Clocking and Sample Rates”.
INITIATING A SEQUENCE
The Register fields associated with running the Control Write Sequencer are described in Table 124.
Note that the operation of the Control Write Sequencer also requires the internal clock SYSCLK to be
configured as described in “Clocking and Sample Rates”.
The Write Sequencer is enabled by setting the WSEQ_ENA bit. The start index of the required
sequence must be written to the WSEQ_START_INDEX field.
The Write Sequencer stores up to 128 register write commands. These are defined in Registers
R4096 to R4607. There are 4 registers used to define each of the 128 possible commands. The value
of WSEQ_START_INDEX selects the registers applicable to the first write command in the selected
sequence.
Setting the WSEQ_START bit initiates the sequencer at the given start index. The Write Sequencer
can be interrupted by writing a logic 1 to the WSEQ_ABORT bit.
The current status of the Write Sequencer can be read using two further register fields - when the
WSEQ_BUSY bit is asserted, this indicates that the Write Sequencer is busy. Note that, whilst the
Control Write Sequencer is running a sequence (indicated by the WSEQ_BUSY bit), full read/write
operations to the Control Registers cannot be supported. (Register access to the Control Write
Sequencer registers, Software Reset registers, PLL/CLKOUT control registers is still supported while
the Control Write Sequencer is running. Unsuccessful I2C interface commands will be indicated to the
host processor by the WM8962 failing to provide the acknowledge, ‘ACK’, indication.)
The index of the current step in the Write Sequencer can be read from the WSEQ_CURRENT_INDEX
field; this is an indicator of the sequencer’s progress. On completion of a sequence, this field holds the
index of the last step within the last commanded sequence.
When the Write Sequencer reaches the end of a sequence, it asserts the WSEQ_DONE_EINT flag in
Register R561 (see “Interrupts”). This flag can be used to generate an Interrupt Event on completion
of the sequence. Note that the WSEQ_DONE_EINT flag is asserted to indicate that the WSEQ is NOT
Busy.
The WM8962 supports the option to automatically power-down the Class D speaker drivers when the
DAC Auto-Mute is triggered, and to re-enable the speaker drivers when audio data is detected. This is
implemented using the Control Write Sequencer, and enabled by setting the WSEQ_AUTOSEQ_ENA
bit. When this bit is set, and the conditions for DAC Auto-Mute are satisfied, the default “Speaker
Sleep” sequence is triggered. When the DAC is un-muted following an Auto-Mute event, the “Speaker
Wake” sequence is triggered. See “Default Sequences” for details of these sequences.
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