W742S81A Datasheet, PDF (8/47 Pages) Winbond – 4 BIT MICROCONTROLLER

W742S81A
111 = ROM page 7 (3800H - 3FFFH)
6.4 Data Memory (RAM)
6.4.1 Architecture
The static data memory (RAM) used to store data is arranged as 2048 × 4 bits. The data RAM is divided
into sixteen banks; each bank has 128 × 4 bits. Executing the MOV DBKR,WR or MOV DBKR,#I
instruction can determine which data bank is used. The data memory can be addressed directly or
indirectly. But the data bank must be confirmed firstly; and the page in the data bank will be done in the
indirect addressing mode, too. In indirect addressing mode, each data bank will be divided into eight pages.
Before the data memory is addressed indirectly, the page which the data memory is in must be confirmed.
The organization of the data memory is shown in Figure 6-2.
2048
addresses
000H
:
07FH
080H
:
0FFH
4 bits
1st data bank
(or Working Registers bank)
2nd data bank
(or Working Registers bank)
3rd data bank
780H
:
7FFH
:
:
16th data bank
2048 * 4 bits
00H
1st data RAM page
:
(or 1st WR page)
0FH
10H
2nd data RAM page
:
(or 2nd WR page)
1FH
20H
3rd data RAM page
:
(or 3rd WR page)
2FH
:
:
70H
8th data RAM page
:
(or 8th WR page)
7FH
Figure 6-2 Data Memory Organization
The 1st and 2nd data bank (00H to 7FH & 80H to FFH) in the data memory can also be used as the
working registers (WR). It is also divided into sixteen pages. Each page contains 16 working registers.
When one page is used as WR, the others can be used as the normal data memory. The WR page can be
switched by executing the MOV WRP,R or MOV WRP,#I instruction. The data memory cannot operate
directly with immediate data, but the WR can do. The relationship between data memory locations and the
page register (PAGE) in indirect addressing mode is described in the next sub-section.
6.4.2 Page Register (PAGE)
The page register is organized as a 4-bit binary register. The bit descriptions are as follows:
3
PAGE
2
1
R/W R/W
Note: R/W means read/write available.
Bit 3 is reserved.
Bit 2, Bit 1, Bit 0 Indirect addressing mode preselect bits:
0
R/W
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