W742S81A Datasheet, PDF (24/47 Pages) Winbond – 4 BIT MICROCONTROLLER

W742S81A
6.15.4 Hold Mode Release Condition Flag (HCF)
The hold mode release condition flag is organized as a 8-bit binary register (HCF.0 to HCF.7). It indicates
by which interrupt source the hold mode has been released, and is loaded by hardware. The HCF can be
read out by the MOVA R, HCFL and MOVA R, HCFH instructions. When any of the HCF bits is "1," the
hold mode will be released and the HOLD instruction is invalid. The HCF can be reset by the CLR EVF or
MOV HEF,#I (HEF = 0) instructions. When EVF and HEF have been reset, the corresponding bit of HCF
is reset simultaneously. The bit descriptions are as follows:
76543210
HCF
RR
RRR
Note: R means read only.
HCF.0 = 1 Hold mode was released by overflow from the divider 0.
HCF.1 = 1 Hold mode was released by underflow from the timer 0.
HCF.2 = 1 Hold mode was released by a signal change at port RC.
HCF.3 is reserved.
HCF.4 = 1 Hold mode was released by overflow from the divider 1.
HCF.5 = 1 Hold mode was released by underflow from the timer 1.
HCF.6 and HCF.7 are reserved.
6.15.5 Event Flag (EVF)
The event flag is organized as a 8-bit binary register (EVF.0 to EVF.7). It is set by hardware and reset by
CLR EVF,#I instruction or the occurrence of an interrupt. The bit descriptions are as follows:
76543210
EVF R
R
RRR
Note: R means read only.
EVF.0 = 1 Overflow from divider 0 occurred.
EVF.1 = 1 Underflow from timer 0 occurred.
EVF.2 = 1 Signal change at port RC occurred.
EVF.3 is reserved.
EVF.4 = 1 Overflow from divider 1 occurred.
EVF.5 & EVF.6 are reserved.
EVF.7 = 1 Underflow from Timer 1 occurred.
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