W742S81A Datasheet, PDF (33/47 Pages) Winbond – 4 BIT MICROCONTROLLER

W742S81A
operand
6.22 LCD Controller/Driver
The W742S81A can directly drive an LCD with 40 segment output pins and 4 common output pins for a
total of 40 × 4 dots. The LCD driving mode is 1/3 bias 1/4 duty. The alternating frequency of the LCD can
be set as Fw/64, Fw/128, Fw/256, or Fw/512. The structure of the LCD alternating frequency (FLCD) is
shown in the Figure 6-14.
Fs or Fosc/128
Fw
(By Dual or single
clock Option)
Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
Fw/64
Fw/128
Fw/256
Fw/512
Selector
FLCD
Figure 6-14 LCD alternating frequency (FLCD) circuit diagram
Fw = 32.768 KHz, the LCD frequency is as shown in the table below.
LCD frequency Fw/64 (512Hz) Fw/128 (256Hz) Fw/256 (128Hz) Fw/512 (64Hz)
1/4 duty
128 Hz
64 Hz
32 Hz
16 Hz
Table 6 The relationship between the FLCD and the duty cycle
Corresponding to the 40 LCD drive output pins, there are 40 LCD data RAM segments. Instructions such
as MOV LPL,R, MOV LPH,R, MOV @LP,R, and MOV R,@LP are used to control the LCD data RAM.
The data in the LCD data RAM are transferred to the segment output pins automatically without program
control. When the bit value of the LCD data RAM is "1," the LCD is turned on. When the bit value of the
LCD data RAM is "0," LCD is turned off. The contents of the LCD data RAM (LCDR) are sent out
through the segment0 to segment39 pins by a direct memory access. The relation between the LCD data
RAM and segment/common pins is shown below.
LCD DATA RAM
LCDR00
LCDR01
:
LCDR26
LCDR27
OUTPUT PIN
SEG0
SEG1
:
SEG38
SEG39
COM3
BIT 3
0/1
0/1
:
0/1
0/1
COM2
BIT 2
0/1
0/1
:
0/1
0/1
COM1
BIT 1
0/1
0/1
:
0/1
0/1
COM0
BIT 0
0/1
0/1
:
0/1
0/1
Publication Release Date: March 2003
- 33 -
Revision A1