W742S81A Datasheet, PDF (11/47 Pages) Winbond – 4 BIT MICROCONTROLLER

W742S81A
Crystal
3.58MHz
or
400KHz
XIN1
or
XOUT1
XIN1
XOUT1
Figure 6-3 System Clock Oscillator Configuration
6.8 Sub-Oscillator
The sub-oscillator is used in dual-clock operation mode. In the sub-oscillator application, just only the
32768 Hz crystal could be connected to XIN2 and XOUT2, and it can not be oscillated in STOP mode.
6.9 Dividers
Each divider is organized as a 14-bit binary up-counter designed to generate periodic interrupts. When the
main oscillator starts action, the Divider0 is incremented by each clock (FOSC). When an overflow occurs,
the Divider0 event flag is set to 1 (EVF.0 = 1). Then, if the Divider0 interrupt enable flag has been set
(IEF.0 = 1), the interrupt is executed, while if the hold release enable flag has been set (HEF.0 = 1), the
hold state is terminated. And the last 4-stage of the Divider0 can be reset by executing CLR DIVR0
instruction.
If the sub-oscillator starts action, the Divider1 is incremented by each clock (Fs in dual-clock mode or
Fosc/128 in single-clock mode). When an overflow occurs, the Divider1 event flag is set to 1 (EVF.4 = 1).
Then, if the Divider1 interrupt enable flag has been set (IEF.4 = 1), the interrupt is executed, while if the
hold release enable flag has been set (HEF.4 = 1), the hold state is terminated. And the last 4-stage of the
Divider1 can be reset by executing CLR DIVR1 instruction. Same as EVF.0, the EVF.4 is set to 1
periodically. But there are two period time (125 mS & 500mS) that can be selected by setting the SCR.3
bit. When SCR.3 = 0 (default), the 500 mS period time is selected; SCR.3 = 1, the 125 mS period time is
selected.
6.10 Dual-clock operation
This operation mode is selected by option code. In the dual-clock mode, the clock source of the LCD
frequency selector should be the sub-oscillator clock (32768 Hz) only. But in the signal-clock mode, the
clock source of the LCD frequency selector will be Fm/128(Fm : main oscillator clock, See figure 6-4).
So before the STOP instruction is executing, the LCD must be turned off in the signal-clock mode or
dual-clock mode.
In this dual-clock mode, the normal operation is performed by generating the system clock from the main-
oscillator clock (Fm). As required, the slow operation can be performed by generating the system clock
from the sub-oscillator clock (Fs). The exchange of the normal operation and the slow operation is
performed by resetting or setting the bit 0 of the System clock Control Register (SCR). If the SCR.0 is reset
Publication Release Date: March 2003
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Revision A1