W742S81A Datasheet, PDF (12/47 Pages) Winbond – 4 BIT MICROCONTROLLER

W742S81A
to 0, the clock source of the system clock generator is main-oscillator clock; if the SCR.0 is set to 1, the
clock source of the system clock generator is sub-oscillator clock. In the dual-clock mode, the main-
oscillator can stop oscillating when the STOP instruction is executing or the SCR.1 is set to 1.
When the SCR is set or reset, we must care the following cases:
1. X000B → X011B: we should not exchange the FOSC from Fm into Fs and disable Fm simultaneously.
We could first exchange the FOSC from Fm into Fs, then disable the main-oscillator. So it should be
X000B→X001B→X011B.
2. X011B → X000B: we should not enable Fm and exchange the FOSC from Fs into Fm simultaneously.
We could first enable the main-oscillator; the 2nd step is calling a delay subroutine to wait the main-
oscillator oscillating stably; then exchange the FOSC from Fs into Fm is the last step. So it should be
X011B→X001B→delay the Fm oscillating stably time→X000B. The suggestion of the Fm oscillating
stably time is 3.5ms for 455K Hz and 0.8ms for 4M Hz.
We must remember that the X010B state is inhibitive, because it will induce the system shutdown.
The organization of the dual-clock operation mode is shown in Figure 6-4.
HOLD
SCR.0
XIN1
XOUT1
Fm
Main Oscillator
Fs
Fosc
System Clock
T1
T2
Generator
T3
SCR.1
T4
enable/disable
STOP
Divider 0
XIN2
XOUT2
Sub-Oscillator
Fosc/128
Dual/Single Colck
Option code is 1/0
LCD Frequency
Selector
F_LCD
Fs or Fosc/128
Divider 1
INT4
HCF.4
SCR.3(14/12 bit)
SCR : System clock Control Register ( default = 00H )
Bit3
Bit1 Bit0
0 : Fosc = Fm
1 : Fosc = Fs
0 : Fm enable
1 : Fm disable
0 : 14 bit
1 : 12 bit
Daul clock operation mode :
- SCR.0=0, Fosc=Fm : SCR.0=1, Fosc=Fs
- Flcd=Fs, In STOP mode LCD does not work.
Figure 6-4 Organization of the dual-clock operation mode
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