W742S81A Datasheet, PDF (13/47 Pages) Winbond – 4 BIT MICROCONTROLLER

W742S81A
6.11 WatchDog Timer (WDT) and WatchDog Timer Register(WDTR)
The watchdog timer (WDT) is organized as a 4-bit up counter designed to prevent the program from
unknown errors. When the corresponding option code bit of the WDT set to 1, the WDT is enabled, and if
the WDT overflows, the chip will be reset. At initial reset, the input clock of the WDT is FOSC/2048. The
input clock of the WDT can be switched to FOSC/16384 (or FOSC/2048) by setting WDTR.3 to 1. The
contents of the WDT can be reset by the instruction CLR WDT. In normal operation, the application
program must reset WDT before it overflows. A WDT overflow indicates that operation is not under
control and the chip will be reset. The WDT overflow period is 1 S when the sub-system clock (Fs) is 32
KHz and WDT clock input is Fs/2048. When the corresponding option code bit of the WDT set to 0, the
WDT function is disabled. The organization of the Divider0 and watchdog timer is shown in Figure 6-5.
Publication Release Date: March 2003
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Revision A1