W89C940 Datasheet, PDF (7/61 Pages) Winbond – ELANC-PCI (TWISTED-PAIR ETHER-LAN CONTROLLER WITH PCI INTERFACE)

W89C940
NAME
MSRDB
MSWRB
MSA[14:0]
RCSB
BPCSB
EECS
NAME
DVCC
DGND
AVCC
NUMBER
49
50
69 - 55
70
71
72
MEMORY INTERFACE
TYPE
DESCRIPTION
O/MOS
O/MOS
O/MOS
Local Memory Read Enable.
An active low signal to enable the local SRAM read.
Local Memory Write Enable.
An active low signal to enable the local SRAM write.
Local
Memory
Address bus for local memory addressing.
Address
Bus.
O/MOS
The MSA14 will be used as the address strobe signal when the size is larger than
32Kx8. If the ROM size is larger than 32Kx8, Boot ROM address !13-A10 is
connected to MSA13-MSA10 and A17-A14 is connected to the latched MSA13-
MSA10. The valid address for the higher significant bits(A14,A15,....) will be stable
before the BPCSB is active low and should be latched by an external data latch
which is triggered by MSA14. The A0 ~ A13 of the BOOT ROM device are
connected to MSA0 ~ MSA13 directly no matter the BOOT ROM size is larger
than 32Kx8 or not.
Memory Chip Select:
The RCSB is active low.
O/MOS
RCSB enables the local memory read/write cycle in conjunction with the MSRDB,
MSWRB pins.
BOOT ROM Chip Select:
BPCSB is active low.
O/MOS
BPCSB enables the BOOT ROM read cycle during the system booting up.
EEPROM Chip Select.
The EEPROM read/write operation will be enabled when EECS is active high.
NUMBER
1, 16, 30,
31, 54
15, 28, 32,
51, 86, 100
81
TYPE
I
I
I
POWER PINS
DESCRIPTION
Digital Power Supply:
5V DC power supply for internal digital logic circuitry.
Digital Ground:
Ground pins for internal digital logic circuitry.
Analog Power Supply:
5V DC power supply for internal analog circuitry.
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