W89C940 Datasheet, PDF (31/61 Pages) Winbond – ELANC-PCI (TWISTED-PAIR ETHER-LAN CONTROLLER WITH PCI INTERFACE)

W89C940
Fast Back-to-Back Transactions
CLK
1
2
3
4
5
6
7
8
FRAME#
AD[31::0]
ADDRESS
DATA
ADDRESS
DATA
C/BE[3::0]#
IRDY#
BUS CMD
BE#'s
BUS CMD
BE#'s
TRDY#
DEVSEL#
STOP#
PAR
Without contention of TRDY#, DEVSEL#, or STOP#, the IDLE states between transactions are removed. It
increase the throughput of the data transaction. If the first transaction is a write cycle and the second transaction
access( can be read or write transaction) to the same target , one IDLE cycle can be removed between
transactions.
Parity
As shown in the figure below, parity is generated at immediately following clock and the internal PERR# is after
PAR. Parity is calculated the same on all PCI transactions regardless of the type or form. Parity covers
AD[31:0] and C/BEB[3:0]# lines regardless of whether or not all lines carry meaningful information. The number
of 1s on AD[31:0], C/BEB[3:0]# and PAR equals an even number. Parity is also calculated at Configuration
phase.
1
2
3
4
5
CLK
FRAME#
AD[31::0]
C_BE#[3::0]
ADDRESS
BUS CMD
DATA
BE#'s
PAR
PERR#
31