W89C940 Datasheet, PDF (59/61 Pages) Winbond – ELANC-PCI (TWISTED-PAIR ETHER-LAN CONTROLLER WITH PCI INTERFACE)

W89C940
AC TIMING
CONDITIONS
0.1uF
Input
Vcc
DEVICE
UNDER
TEST
SW1 (Note 3)
RL = 2.2K
Output
CL (Note 1,2)
TEST
PARAMETER
TEST CONDITION
Supply voltage (V_DD/V_SS)
Temperature
5V±5%
25°C/70°C
Input Test Pattern Levels (TTL/CMOS)
GND to 4.0V
Input Rise and Fall Times (TTL/CMOS)
5nS
Input and Output Pattern Reference Level
(TTL/CMOS)
1.5V
Input Waveform Level (Diff)
-350 to -1315 mV
Input and Output Waveform
Reference Levels
50% Point of the Differential
Tristate Reference Levels
Float (V) + 0.5V
Note 1: These parameters are specified by design and are not tested.
OUTPUT LOAD
The above specifications are valid only if the mandatory isolations are correctly employed and all differential
signals are taken to the AUI of the pulse transformer.
Note 1: Load capacitance employed depends on output type.
For 3SL, MOS, TPI, AUI: CL=50 pF.
For 3SH, OCH: CL=240 pF.
Note 2: Specifications which measure delays from an active state to a High-Z state are not guaranteed by production test, but are characterized
using 240 pF and are correlated to determine true driver turn-off time by eliminating inherent R-C delay times in measurements.
Note 3: SW1=Open for push pull outputs during timing test.
SW1=VCC for VOL test.
SW1=GND for VOH test.
SW1=VCC for High-Z to active low and active low to High-Z measurements.
SW1=GND for High-Z to active high and active high to High-Z measurements.
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