W89C940 Datasheet, PDF (47/61 Pages) Winbond – ELANC-PCI (TWISTED-PAIR ETHER-LAN CONTROLLER WITH PCI INTERFACE)

W89C940
T2
clock n+6 to MSA valid
25
28
30
nsec
T3
clock n+7 to RCSB deasserted time
10
15
20
nsec
T4
clock n+4 to MSRDB valid
22
27
30
nsec
T5
clock n+7 to MSRDB deasserted time
15
20
25
nsec
T6
MSD setup tim to clock n+6
7
nsec
T7
MSD hold time from clock n+6
0
nsec
Remote Read Word Access Cycle
0
1
2
3
CLK
FRAME#
AD[31::0]
C_BE#[3:0]
IRDY#
ADDRESS
BUS CMD
TRDY#
DEVSEL#
MSA0-13
RCSB
MSRDB
MSWRB
MSD0-7
(Read)
n+4 n+5 n+6
n+8 ^{n+9 n+10} n+11
BE#'s
DATA
T2
T8
T1
T3
T5
T4
T6
T7
T6 _T7
Note: 1) The other timing requirements for PCI signal are as the read transaction timing.
2) n=0,1,2,3,..... when local DMA get the control of the bus, PCI bus will insert wait state.
Wait state number is n.
SYMBOL
DESCRIPTION
MIN
T1
clock n+4 to RCSB and MSA valid (note
20
2)
T2
clock n+6 to MSA valid
25
T3
clock n+7 to RCSB deasserted time
10
T4
clock n+4 to MSRDB valid
22
T5
clock n+7 to MSRDB deasserted time
15
TYPICAL
25
28
15
27
20
MAX
30
30
20
30
25
UNIT
nsec
nsec
nsec
nsec
nsec
47