W89C940 Datasheet, PDF (24/61 Pages) Winbond – ELANC-PCI (TWISTED-PAIR ETHER-LAN CONTROLLER WITH PCI INTERFACE)

W89C940
PHY1
0
0
0
0
0
1
1
1
1
1
PHY0
0
0
0
1
1
0
0
1
1
1
LNKEN
1
0
0
1
0
1
0
1
0
0
GDLNK
1
1
0
1
0 or 1
1
0 or 1
1
1
0
Auto Switching Function
disabled, keep at UTP
enabled, keep at UTP
enabled, UTP switch to BNC or AUI
disabled, keep at AUI
disabled, keep at AUI
disabled, keep at AUI
disabled, keep at AUI
disabled, keep at UTP
enabled, keep at UTP
enabled, UTP switch to BNC or AUI
SIGNATURE REGISTER
The signature register can be read by PCI Configuration Cycle with address 40H. The consecutive read will get
a data pattern 88H, 00H, 88H, 00H,.... if byte enable (C_BEB#) is asserted. A write operation will have no effect
on the content of this signature register.
Early Interrupt Function
1. Background:
W89C940 includes some control circuit and status register bits to generate interrupt signal early during
receiving packets. Besides traditional interrupt generated at incoming packet end, W89C940 can generate
interrupt when received packet bytes reach Early Interrupt Threshold and early interrupt function is enabled.
2. Register List:
Registers
IO Address
EIR_EN
Page 0
Base+0bh
[0]
EIR_MASK
Page 0
Base+0bh
[1]
EIR_STATU
S
Page 0
Base+0bh
[7]
Descriptions
Early Interrupt Enable Register: Read/Write
Asserted high to enable Early Interrupt Function. Deasserted to
disable Early Interrupt Function. To program Receive Control
Register (RCR) to monitor mode or Data Configuration Register
(DCR) to Loopback mode will also disable Early Interrupt
Function. Initial value after Power-on Reset is 0. Read once
write.
Early Interrupt Mask Register: Read/Write
Asserted high to initiate an interrupt on INTA# of PCI local bus
when an Early Interrupt Event occured. Deasserted this register
will mask an interrupt generated. Deasserted this register does
not disable Early Interrupt Status Register. Initial value after
Power-on Reset is 0.Read once write.
Early Interrupt Status Register: Read/Write
Asserted high when the byte count of incoming frame reaches
Early Interrupt Threshold with correct destination address (DS), in
the enable mode of Early Interrupt Function. Write 1 to clear
EIR_STATUS. Initial value after Power-on Reset is 0. Read
once write.
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