W89C940 Datasheet, PDF (54/61 Pages) Winbond – ELANC-PCI (TWISTED-PAIR ETHER-LAN CONTROLLER WITH PCI INTERFACE)

W89C940
32KX8-220 BPROM/ FLASH MEMORY
Read cycle
0
CLK
123
4 ₅ 6 7 ₈ 9 _{10 11 12 13 14 15} 16 17 18 19 20 21 22 23 24 25 26
FRAME#
AD[31::0]
C_BEB[3:0]#
IRDY#
TRDY#
DEVSEL#
MSA14/L
MSA[9:0]
MSA[13:10]
BPCSB
MSRDB
MSD[7:0]
T2
T1
T3
T6
T7
T9
T4
T10
T11
T12
T5
T8
T9
T10
T11
T12
SYMBOL DESCRIPTION
MIN
TYPICAL
T1
clock 4 to MSA14/L valid
8
13
T2
clock 5 to MSA14/L deasserted time
8
13
T3
clock 6 to MSA bus valid
8
13
T4
clock 14 to MSA bus valid
8
13
T5
clock 23 to MSA deasserted
8
13
T6
clock 4 to MSA high nibble valid
8
13
T7
clock 6 to BPCSB valid
15
20
T8
clock 25 to BPCSB deasserted
7
12
T9
clock 8/ clock 17 to MSRDB asserted time
15
20
T10
clock 13/ clock 22 to MSRDB deasserted time
8
13
T11
MSD setup time from clock 13
7
T12
MSD hold time from clock 15
0
Note: 1) The other timing requirements for PCI signal are as the read transaction timing.
2) BPROM/FLASH memory access could be byte, word or double word access.
The timing is the same.
MAX
18
18
18
18
18
18
25
17
25
18
UNIT
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
54