W89C940 Datasheet, PDF (50/61 Pages) Winbond – ELANC-PCI (TWISTED-PAIR ETHER-LAN CONTROLLER WITH PCI INTERFACE)

W89C940
CLK
FRAME#
AD[31::0]
C_BE[3:0]#
IRDY#
TRDY#
DEVSEL#
MSA0-13
RCSB
MSRDB
MSWRB
MSD0-7
0
1
2
3
n+5 n+6 n+7 n+8 n+9 n+10 n+11
ADDRESS
BUS CMD
DATA
BE#'s
DATA
BE#'s
T2
T6
T1
T10
T11
T5
T3 _T4
T3 _T4
T7
T8
T9
Note: 1) The other timing requirements for PCI signal are as the read transaction timing.
2) n=0,1,2,3,..... when local DMA get the control of the bus, PCI bus will insert wait state.
Wait state number is n.
SYMBOL
DESCRIPTION
MIN
TYPICAL
MAX UNIT
T1
Clock n+5 to MSA, RCSB, and
17
MSD valid (note 2)
22
27
nsec
T2
clock n+7 to MSA valid
14
19
24
nsec
T3
clock n+6 to MSWRB valid
9
14
19
nsec
T4
Write pulse width
4
9
14
nsec
T5
clock n+10 to RCSB deasserted
7
12
17
nsec
T6
clock n+9 to MSA deasserted
14
19
24
nsec
T7
clock n+5 to MSD valid
17
22
27
nsec
T8
clock n+7 to MSD deasserted
16
21
26
nsec
T9
clock n+10 to MSD deasserted
8
13
18
nsec
T10 MSA change to MSWRB
deasserted time
T11 MSA change to MSWRB
deasserted time
50