W89C940 Datasheet, PDF (26/61 Pages) Winbond – ELANC-PCI (TWISTED-PAIR ETHER-LAN CONTROLLER WITH PCI INTERFACE)

W89C940
CLK
1
2
3
4
5
6
7
8
FRAME#
AD[31::0]
C_BE[3:0]#
ADDRESS
BUS CMD
BE#'s
DATA
IRDY#
TRDY#
DEVSEL#
STOP#
PAR
The transaction is initiated by FRAME# , the address is asserted and bus read command of C/BE[3:0]# is also
asserted. This phase is called address phase. IRDY# (Initiator Ready) is asserted by master after address
phase. Target initiate TRDY#( Target Ready) and assert valid data on the bus. The DEVSEL# means the target
is addressed and respond to the master device. The data transaction is happened on both IRDY# and TRDY#
are asserted on the same clock edge that is called data phase. During the data phase, the BE (Byte Enable)
indicate the data length of the data. If it is a double word, 32 bits, the BE will be 0000. If data is a word, the BE
will be 1100 or 0011
If the host send the memory read command in burst mode, W89C940 accept the first data phase
access and then reject the further data access request with retry disconnection. Only one data phase
is allowed for transaction.
Write Transaction ( I/O and Memory Write)
The write transaction is like read transaction, the FRAME# initiate the transaction with address phase and the
data is written in data phase. The data could be asserted directly after address phase. It does not need a WAIT
state for avoiding bus contention. The transaction is ended when the FRAME#, IRDY#, TRDY# and DEVSEL#
are deasserted. If the host send the memory read command in burst mode, W89C940 accept the first data
phase access and then reject the further data access request with Retry disconnection. Only one data phase is
allowed for transaction.
The write transaction is as shown in the figure
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