W89C940 Datasheet, PDF (20/61 Pages) Winbond – ELANC-PCI (TWISTED-PAIR ETHER-LAN CONTROLLER WITH PCI INTERFACE)

W89C940
ROM-Base-Address Register
Bit
31~24 23~16 15~8 7~0
Attribute R/W R/W R/W R/W
Initial Value FFH FFH 80H 01H
The W89C940 supports 8Kx8, 16Kx8, 32Kx8, 64Kx8, 128Kx8 and 256Kx8 ROM address decoding function.
For a 8Kx8 ROM application, the upper 19 bits of this register correspond to the upper 19 bits of the expansion
ROM base address. The lower 13 bits of this register correspond to the size of the expansion ROM. Those bits
correspond to the size of the expansion ROM are determined by MCR bit 5, bit 6 and bit 7 and can not be
writable by the system configuration write command. The device independent configuration software can only
determined the bits corresponding to the base address. The following table describe the relationship between
the addressing bus, sizing bits and the MCR bit 5/6/7.
MCR.7
0
0
0
1
1
1
1
MCR.6
0
1
1
0
0
1
1
MCR.5
X
0
1
0
1
0
1
Addressing Bits
None
31~13
31~14
31~15
31~16
31~17
31~18
Sizing Bits
None
12~0
13~0
14~0
15~0
16~0
17~0
ROM Size
No BOOT ROM
8Kx8
16Kx8
32Kx8
64Kx8
128Kx8
256Kx8
The device independent configuration software can only determined the addressing bits. The bit 0 of the ROM
base address register will be reset "0" by W89C940 if the MCR is set as "No BOOT ROM", i.e. BPS0=0,
BPS1=0 and BPS2=0. The bit 0 of the ROM base address register will be set "1" if the MCR is programmed as
there is an expansion ROM device add-on the LAN adapter. The initial value of FFFF8001H indicates that there
is a 32Kx8 expansion ROM device existing. The initial value is changed according to the BOOT ROM size
selection in the MCR (Mode Configuration Register).
Interrupt Line Register
This register is a readable and writable register. The POST software of system could write the routing
information into this register as it initializes and configures the system. The value in this register tells which
input of the system interrupt controllers the device's interrupt pin i connected to. Device drivers and operating
systems can use this information to determine priority and vector information. For x86 based PCs, the value in
this register correspond to IRQ numbers (0-15) of the standard dual 8259 configuration. The value 255 is
defined as meaning "unknown" or "no connection" to the interrupt controller. Values between 15 and 255 are
reserved.
Interrupt Pin Register
The W89C940 use the INTA# as its interrupt pin. The content of this register is fixed into "01".
Min-Gnt Register
It is used for specifying how long a burst period the device needs assuming a clock rate of 33MHz. The content
of this register will be updated after power on by the EEPROM load operation. The Min-Gnt should be
programmed into the 17th byte of the EEPROM for power on auto loading.
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