W49V002A Datasheet, PDF (7/32 Pages) Winbond – 256K x 8 CMOS FLASH MEMORY WITH LPC INTERFACE

Preliminary W49V002A
STANDARD LPC MEMORY CYCLE DEFINITION
FIELD
NO. OF CLOCKS
DESCRIPTION
Start
1
"0000b" appears on LPC bus to indicate the initial
Cycle Type & Dir
1
"010Xb" indicates memory read cycle; while "011xb" indicates memory write
cycle. "X" mean don't have to care.
TAR
2
Turned Around Time
Addr.
8
Address Phase for Memory Cycle. LPC supports the 32 bits address
protocol. The addresses transfer most significant nibble first and least
significant nibble last. (i.e. Address[31:28] on LAD[3:0] first , and
Address[3:0] on LAD[3:0] last.)
Sync.
N
Synchronous to add wait state. "0000b" means Ready, "0101b" means
Short Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b"
means error, and other values are reserved.
Data
2
Data Phase for Memory Cycle. The data transfer least significant nibble first
and most significant nibble last. (i.e. DQ[3:0] on LAD[3:0] first , then DQ[7:4]
on LAD[3:0] last.)
Note: 1. For detail related LPC specification, please refer to Intel LPC spec. 1.0 or later.
Publication Release Date: April 2001
-7-
Revision A1