W49V002A Datasheet, PDF (6/32 Pages) Winbond – 256K x 8 CMOS FLASH MEMORY WITH LPC INTERFACE

Preliminary W49V002A
TABLE OF OPERATING MODES
Operating Mode Selection - Programmer Mode
(VHH = 12V ± 5%)
MODE
#OE #WE #RESET
Read
VIL
VIH
VIH AIN
Write
VIH
VIL
VIH AIN
Standby
X
X
VIL X
Write Inhibit
VIL
X
VIH X
X
VIH
VIH X
Output Disable
VIH
X
VIH X
PINS
ADDRESS
DQ.
Dout
Din
High Z
High Z/DOUT
High Z/DOUT
High Z
Operating Mode Selection - LPC Mode
Operation modes in LPC interface mode are determined by "cycle type" when it is selected. When it is
not selected, its outputs (LAD[3:0]) will be disable. Please reference to the "Standard LPC Memory
Cycle Definition".
TABLE OF COMMAND DEFINITION
COMMAND
NO. OF 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE
DESCRIPTION
Read
Chip Erase
Cycles
1
6
Addr. Data
A_IN D_OUT
5555 AA
Addr. Data
2AAA 55
Addr. Data
5555 80
Addr. Data
5555 AA
Addr. Data
2AAA 55
Addr. Data
5555 10
Sector Erase
6
5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA 30
Byte Program
Boot Block Lockout
Product ID Entry
Product ID Exit ⁽¹⁾
Product ID Exit ⁽¹⁾
4
5555 AA 2AAA 55 5555 A0 A_IN D_IN
6
5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40
3
5555 AA 2AAA 55 5555 90
3
5555 AA 2AAA 55 5555 F0
1
XXXX F0
Note: 1. The cycle means the write command cycle not the LPC clock cycle.
2. The Column Address / Row Address are mapped to the Low / High order Internal Address. i.e. Column Address
A[10:0] are mapped to the internal A[10:0], Row Address A[6:0] are mapped to the internal A[17:11]
3. Address Format: A14−A0 (Hex); Data Format: DQ7-DQ0 (Hex)
4. Either one of the two Product ID Exit commands can be used.
5. SA : Sector Address
SA = 3C000h to 3FFFFh for Boot Block
SA = 3A000h to 3BFFFh for Parameter Block1
SA = 38000h to 39FFFh for Parameter Block2
SA = 30000h to 37FFFh for Main Memory Block1
SA = 2XXXXh for Main Memory Block2
SA = 1XXXXh for Main Memory Block3
SA = 0XXXXh for Main Memory Block4
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