W49V002A Datasheet, PDF (27/32 Pages) Winbond – 256K x 8 CMOS FLASH MEMORY WITH LPC INTERFACE

Preliminary W49V002A
Timing Waveforms for LPC Interface Mode, continued
Chip Erase Timing Diagram
CLK
#RESET
#LFRAM
LAD[3:0]
1st Start
Memory
Write
Cycle
Address
Data
TAR
Sync
0000b 011Xb A[31:28] A[27:24] A[23:20] A[19:16]
X101b
0101b
0101b
0101b
1010b
1010b
1111b Tri-State
0000b
TAR
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
Load Data "AA"
in 2 Clocks
Write the 1st command to the device in LPC mode.
2 Clocks 1 Clock
CLK
#RESET
#LFRAM
2nd Start
Memory
Write
Cycle
Address
Data
TAR
Sync
LAD[3:0]
0000b 011Xb A[31:28] A[27:24] A[23:20] A[19:16]
X010b
1010b 1010b
1010b
0101b
0101b
1111b Tri-State
0000b
TAR
1 Clock 1 Clock
Load Address "2AAA" in 8 Clocks
Load Data "55"
in 2 Clocks
2 Clocks 1 Clock
Write the 2nd command to the device in LPC mode.
CLK
#RESET
#LFRAM
3rd Start
Memory
Write
Cycle
Address
Data
TAR
Sync
LAD[3:0]
0000b 011Xb A[31:28] A[27:24] A[23:20] A[19:16]
X101b 0101b
0101b
0101b 0000b
1000b
1111b Tri-State
0000b
TAR
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
Load Data "80"
in 2 Clocks
Write the 3rd command to the device in LPC mode.
2 Clocks 1 Clock
CLK
#RESET
#LFRAM
LAD[3:0]
4th Start
0000b
Memory
Write
Cycle
011Xb
A[31:28]
A[27:24]
Address
A[23:20] A[19:16]
X101b
0101b 0101b
0101b
Data
1010b
1010b
TAR
1111b Tri-State
Sync
0000b
TAR
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
Load Data "AA"
in 2 Clocks
Write the 4th command to the device in LPC mode.
2 Clocks 1 Clock
CLK
#RESET
#LFRAM
5th Start
Memory
Write
Cycle
Address
Data
TAR
Sync
LAD[3:0]
0000b 011Xb A[31:28] A[27:24] A[23:20] A[19:16]
X010b 1010b
1010b
1010b
0101b
0101b 1111b Tri-State
0000b
TAR
1 Clock 1 Clock
Load Address "2AAA" in 8 Clocks
Load Data "55"
in 2 Clocks
2 Clocks 1 Clock
Write the 5th command to the device in LPC mode.
Start next
command
1 Clock
Start next
command
1 Clock
Start next
command
1 Clock
Start next
command
1 Clock
Start next
command
1 Clock
CLK
#RESET
#LFRAM
LAD[3:0]
6th Start
0000b
Memory
Write
Cycle
011Xb
A[31:28]
A[27:24]
Address
A[23:20] A[19:16]
X101b
0101b
0101b
0101b
Data
0000b
0001b
TAR
1111b Tri-State
Sync
0000b
Internal
erase start
TAR
Internal
erase start
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
Load Data "10"
in 2 Clocks
2 Clocks
1 Clock
Write the 6th command to the device in LPC mode.
All the address loaded should be within the top 4MByte,FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000.
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Publication Release Date: April 2001
Revision A1