W49V002A Datasheet, PDF (29/32 Pages) Winbond – 256K x 8 CMOS FLASH MEMORY WITH LPC INTERFACE

Timing Waveforms for LPC Interface Mode, continued
GPI Register Readout Timing Diagram
Preliminary W49V002A
CLK
#RESET
#LFRAM
LAD[3:0]
Start
0000b
Memory
Read
Cycle
010Xb A[31:28] ^A[27:24]
Address
A[23:20] A[19:16] 0000b
0001b
0000b
0000b
TAR
Sync
1111b Tri-State 0000b
Data
D[3:0] D[7:4]
TAR
1 Clock 1 Clock
Load Address "FFBC0100(hex)" in 8 Clocks
2 Clocks 1 Clock Data out 2 Clocks
Note: Read the DQ[4:0] to capture the states(High or Low) of the GPI[4:0] input pins. The DQ[7:5] are reserved pins.
Next Start
0000b
1 Clock
Reset Timing Diagram
VDD
CLK
#RESET
LAD[3:0]
#LFRAM
TPRST
TKRST
TRSTP
TRST
F
TRST
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Publication Release Date: April 2001
Revision A1