W49V002A Datasheet, PDF (22/32 Pages) Winbond – 256K x 8 CMOS FLASH MEMORY WITH LPC INTERFACE

Preliminary W49V002A
TIMING WAVEFORMS FOR LPC INTERFACE MODE
Read Cycle Timing Diagram
CLK
#RESET
#LFRAM
LAD[3:0]
T_CYC
T_SU T_HD
T_SU T_HD
Start
Memory
Read
Cycle
Address
0000b _{010Xb A[31:28]} A[27:24] _{A[23:20] A[19:16] A[15:12] A[11:8] A[7:4]}
T_KQ
A[3:0]
TAR
Sync
1111b Tri-State 0000b
Data
D[3:0] D[7:4]
1 Clock 1 Clock Load Address in 8 Clocks, the address should be within the top 4MByte,
FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000.
2 Clocks
1 Clock Data out 2 Clocks
TAR
Next Start
0000b
1 Clock
Write Cycle Timing Diagram
CLK
#RESET
#LFRAM
LAD[3:0]
TCYC
Memory
Write
Start Cycle
Address
0000b 011Xb _A[31:28] A[27:24] _{A[23:20] A[19:16] A[15:12] A[11:8]}
A[7:4]
A[3:0]
TSU THD
Data
D[3:0] D[7:4]
TAR
Sync
1111b Tri-State 0000b
1 Clock 1 Clock Load Address in 8 Clocks, the address should be within the top 4MByte,
Load Data in 2 Clocks
FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000.
2 Clocks
1 Clock
TAR
Next Start
0000b
1 Clock
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