W49V002A Datasheet, PDF (23/32 Pages) Winbond – 256K x 8 CMOS FLASH MEMORY WITH LPC INTERFACE

Preliminary W49V002A
Program Cycle Timing Diagram
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
1st Start
Write
Cycle
Address
0000b 011Xb
1 Clock 1 Clock
A[31:28] A[27:24] A[23:20] A[19:16]
X101b
0101b
Load Address "5555" in 8 Clocks
0101b
Data
TAR
Sync
0101b 1010b 1010b ^{1111b Tri-State 0000b}
Load Data "AA" in 2 Clocks 2 Clocks
1 Clock
Write the 1st command to the device in LPC mode.
CLK
#RESET
TAR
Start next
command
1 Clock
#LFRAM
LAD[3:0]
Memory
Write
2nd Start Cycle
Address
Data
0000b 011Xb
1 Clock 1 Clock
A[31:28] A[27:24] A[23:20] A[19:16] X010b 1010b
Load Address "2AAA" in 8 Clocks
1010b
1010b
0101b 0101b
Load Data "55"
in 2 Clocks
Write the 2nd command to the device in LPC mode.
TAR
Sync
1111b Tri-State 0000b
2 Clocks
1 Clock
CLK
#RESET
TAR
Start next
command
1 Clock
#LFRAM
LAD[3:0]
Memory
3rd Start
Write
Cycle
0000b 011Xb
1 Clock 1 Clock
A[31:28]
A[27:24]
Address
Data
A[23:20] A[19:16]
X101b 0101b
0101b 0101b 0000b 1010b
Load Address "5555" in 8 Clocks
Load Data "A0"
in 2 Clocks
Write the 3rd command to the device in LPC mode.
TAR
Sync
1111b Tri-State 0000b
2 Clocks
1 Clock
CLK
#RESET
TAR
Start next
command
1 Clock
#LFRAM
LAD[3:0]
Memory
4th Start
Write
Cycle
0000b 011Xb
A[31:28]
A[27:24]
1 Clock 1 Clock
Address
A[23:20] A[19:16] A[15:12] A[11:8]
Load Ain in 8 Clocks
A[7:4]
Data
TAR
Sync
A[3:0]
D[3:0]
D[7:4]
Load Din in 2 Clocks
1111b Tri-State 0000b
2 Clocks
1 Clock
Internal
program start
TAR Internal
program start
Write the 4th command(target location to be programmed) to the device in LPC mode.
All the address loaded should be within the top 4MByte,FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000.
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Publication Release Date: April 2001
Revision A1