W49V002A Datasheet, PDF (21/32 Pages) Winbond – 256K x 8 CMOS FLASH MEMORY WITH LPC INTERFACE

Preliminary W49V002A
LPC INTERFACE MODE AC CHARACTERISTICS
AC Test Conditions
PARAMETER
Input Pulse Levels
Input Rise/Fall Slew Rate
Input/Output Timing Level
Output Load
CONDITIONS
0.6 VDD to 0.2 VDD
1 V/nS
0.4VDD / 0.4VDD
1 TTL Gate and CL = 10 pF
AC Test Load and Waveform
DOUT
10 pF
25 _Ω
Test when output from low to high
D_OUT
10 pF
25 _Ω
V DD
Input
Output
0.6V _DD
0.2V _DD
0.4V_DD
0.4V _DD
Test Point
Test Point
Test when output from high to low
Read/Write Cycle Timing Parameters
(VDD = 3.3V ± 5%, V GND = 0V, TA = 0 to 70° C)
PARAMETER
SYM.
Clock Cycle Time
Input Set Up Time
Input Hold Time
Clock to Data Valid
TCYC
TSU
THD
TKQ
W49V002A
MIN.
MAX.
30
-
7
-
0
-
-
11
UNIT
nS
nS
nS
nS
Reset Timing Parameters
PARAMETER
Vdd stable to Reset Active
Clock Stable to Reset Active
Reset Pulse Width
Reset Active to Output Float
Reset Inactive to Input Active
SYMBOL
TPRST
TKRST
TRSTP
TRSTF
TRST
MIN.
1
100
100
-
1
TYP.
-
-
-
-
-
MAX.
-
-
-
50
-
Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is input high and (b) low level signal's reference level is input low.
Ref. to the AC testing condition.
UNIT
mS
µS
nS
nS
µS
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Publication Release Date: April 2001
Revision A1