W49V002A Datasheet, PDF (24/32 Pages) Winbond – 256K x 8 CMOS FLASH MEMORY WITH LPC INTERFACE

Timing Waveforms for LPC Interface Mode, continued
#DATAPolling Timing Diagram
Preliminary W49V002A
CLK
#RESET
#LFRAM
LAD[3:0]
CLK
#RESET
#LFRAM
LAD[3:0]
CLK
Memory
Write
1st Start Cycle
Address
Data
TAR
Sync
0000b 011Xb _An[31:28] An[27:24] _{An[23:20] An[19:16] An[15:12] An[11:8]} An[7:4]
An[3:0] ^{Dn[3:0] Dn[7:4]} 1111b Tri-State 0000b
TAR
1 Clock 1 Clock
Load Address "An" in 8 Clocks
Load Data "Dn"
in 2 Clocks
2 Clocks
Write the last command(program or erase) to the device in LPC mode.
1 Clock
XXXXb
Start
0000b
Memory
Read
Cycle
Address
010Xb _An[31:28] An[27:24] _{An[23:20] An[19:16] An[15:12]} An[11:8]
1 Clock 1 Clock
Load Address in 8 Clocks
An[7:4]
An[3:0]
TAR
Sync
Data
1111b Tri-State 0000b XXXXb Dn7,xxx
2 Clocks 1 Clock Data out 2 Clocks
TAR
Read the DQ7 to see if the internal write complete or not.
#RESET
#LFRAM
LAD[3:0]
Start
0000b
Memory
Read
Cycle
Address
010Xb An[31:28] An[27:24] An[23:20] An[19:16] _{An[15:12] An[11:8]}
1 Clock 1 Clock
Load Address in 8 Clocks
An[7:4]
An[3:0]
TAR
Sync
1111b Tri-State 0000b
Data
XXXXb Dn7,xxx
2 Clocks 1 Clock Data out 2 Clocks
TAR
When internal write complete, the DQ7 will equal to Dn7.
All the address loaded should be within the top 4MByte,FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000.
Start next
command
0000b
1 Clock
Next Start
0000b
1 Clock
Next Start
0000b
1 Clock
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