W83697HF Datasheet, PDF (56/167 Pages) Winbond – WINBOND I/O

W83697HF/F
TABLE 4-1 UART Register Bit Map
Register Address Base
Bit Number
0
1
2
3
4
5
6
7
+0
BDLAB = 0
Receiver
Buffer
Register
(Read Only)
+0
Transmitter
BDLAB = 0 ^{Buffer Register}
(Write Only)
+ 1 Interrupt Control
BDLAB = 0 ^Register
RBR
TBR
ICR
+2
Interrupt Status ISR
Register
(Read Only)
+2
UART FIFO UFR
Control
Register
(Write Only)
+3
UART Control UCR
Register
+4
Handshake HCR
Control
Register
+5
UART Status USR
Register
RX Data
Bit 0
TX Data
Bit 0
RBR Data
Ready
Interrupt
Enable
(ERDRI)
"0" if
Interrupt
Pending
FIFO
Enable
Data
Length
Select
Bit 0
(DLS0)
Data
Terminal
Ready
(DTR)
RBR Data
Ready
(RDR)
RX Data
Bit 1
TX Data
Bit 1
TBR
Empty
Interrupt
Enable
(ETBREI)
Interrupt
Status
Bit (0)
RCVR
FIFO
Reset
Data
Length
Select
Bit 1
(DLS1)
Request
to
Send
(RTS)
Overrun
Error
(OER)
RX Data
Bit 2
TX Data
Bit 2
USR
Interrupt
Enable
(EUSRI)
Interrupt
Status
Bit (1)
XMIT
FIFO
Reset
Multiple
Stop Bits
Enable
(MSBE)
Loopback
RI
Input
Parity Bit
Error
(PBER)
+6
Handshake HSR
Status Register
+7
+0
BDLAB = 1
+1
BDLAB = 1
User Defined
Register
Baudrate
Divisor Latch
Low
Baudrate
Divisor Latch
High
UDR
BLL
BHL
CTS
Toggling
(TCTS)
Bit 0
Bit 0
Bit 8
DSR
Toggling
(TDSR)
Bit 1
Bit 1
Bit 9
RI Falling
Edge
(FERI)
Bit 2
Bit 2
Bit 10
RX Data
Bit 3
TX Data
Bit 3
HSR
Interrupt
Enable
(EHSRI)
Interrupt
Status
Bit (2)**
DMA
Mode
Select
Parity
Bit
Enable
(PBE)
IRQ
Enable
No Stop
Bit
Error
(NSER)
DCD
Toggling
(TDCD)
Bit 3
Bit 3
Bit 11
RX Data
Bit 4
RX Data RX Data RX Data
Bit 5
Bit 6
Bit 7
TX Data
Bit 4
TX Data
Bit 5
TX Data
Bit 6
0
0
0
TX Data
Bit 7
0
0
Reserved
Even
Parity
Enable
(EPE)
Internal
Loopback
Enable
0
Reversed
Parity
Bit Fixed
Enable
PBFE)
0
FIFOs
FIFOs
Enabled Enabled
**
**
RX
RX
Interrupt Interrupt
Active Level Active Level
(LSB)
(MSB)
Set
Baudrate
Silence
Enable
(SSE)
Divisor
Latch
Access Bit
(BDLAB)
0
0
Silent
Byte
Detected
(SBD)
Clear
to Send
(CTS)
Bit 4
TBR
Empty
(TBRE)
Data Set
Ready
(DSR)
Bit 5
TSR
Empty
(TSRE)
Ring
Indicator
(RI)
Bit 6
RX FIFO
Error
Indication
(RFEI) **
Data Carrier
Detect
(DCD)
Bit 7
Bit 4
Bit 5
Bit 6
Bit 7
Bit 12
Bit 13
Bit 14
Bit 15
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 Mode.
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Publication Release Date: Feb. 2002
Revision 0.70