W9425G6JH_13 Datasheet, PDF (48/52 Pages) Winbond – 4 M x 4 BANKS x 16 BITS DDR SDRAM

W9425G6JH
12.21 4 Bank Interleave Read Operation (CL = 2, BL = 2)
CLK
CLK
tRRD
tRRD
tRC(a)
tRRD
tRRD
CMD
ACTa
DQS
DQ
ACTb
tRCD(a)
tRAS(a)
ACTc READAa ACTd READAb ACTa READAc
tRCD(b)
tRAS(b)
tRP
tRCD(c)
tRAS(c)
tRCD(d)
tRAS(d)
Preamble
CL(a)
Postamble Preamble
CL(b)
Q0a Q1a
Q0b Q1b
ACTa/b/c/d : Bank Act. CMD of bank a/b/c/d
READAa/b/c/d : Read with Auto Pre.CMD of bank a/b/c/d
APa/b/c/d : Auto Pre. of bank a/b/c/d
APa
APb
12.22 4 Bank Interleave Read Operation (CL = 2, BL = 4)
CLK
CLK
tRRD
tRRD
tRC(a)
tRRD
tRRD
CMD
ACTa
DQS
DQ
ACTb READAa
tRCD(a)
tRAS(a)
ACTc READAb ACTd READAc ACTa
tRCD(b)
tRAS(b)
tRCD(c)
tRAS(c)
tRP(a)
tRCD(d)
tRAS(d)
READAd
Preamble
CL(a)
CL(b)
CL(c)
Q0a Q1a Q2a Q3a Q0b Q1b Q2b Q3b Q0c Q1c
ACTa/b/c/d : Bank Act. CMD of bank a/b/c/d
READAa/b/c/d : Read with Auto Pre.CMD of bank a/b/c/d
APa/b/c/d : Auto Pre. of bank a/b/c/d
APa
APb
APc
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Publication Release Date: Aug. 27, 2013
Revision A03