W9425G6JH_13 Datasheet, PDF (25/52 Pages) Winbond – 4 M x 4 BANKS x 16 BITS DDR SDRAM

W9425G6JH
10.5 DC Characteristics
SYM.
PARAMETER
IDD0
IDD1
IDD2P
IDD2N
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
Operating current: One Bank Active-Precharge;
tRC = tRC min; tCK = tCK min;
DQ, DM and DQS inputs changing once per clock cycle;
Address and control inputs changing once every two clock cycles
Operating current: One Bank Active-Read-Precharge;
Burst = 4; tRC = tRC min; CL = 3; tCK = tCK min; IOUT = 0 mA;
Address and control inputs changing once per clock cycle.
Precharge Power Down standby current:
All Banks Idle; Power down mode;
CKE  VIL max; tCK = tCK min; Vin = VREF for DQ, DQS and DM
Idle standby current:
CS  VIH min; All Banks Idle; CKE  VIH min; tCK = tCK min;
Address and other control inputs changing once per clock cycle;
Vin  VIH min or Vin  VIL max for DQ, DQS and DM
Precharge floating standby current:
CS  VIH min; all banks idle; CKE  VIH min;
Address and other control inputs changing once per clock cycle;
VIN = VREF for DQ, DQS and DM.
Precharge quiet standby current:
CS  VIH min; all banks idle; CKE > VIH min;
Address and other control inputs stable at > VIH min or  VIL max;
Vin = VREF for DQ, DQS and DM.
Active Power Down standby current:
One Bank Active; Power down mode;
CKE  VIL max; tCK = tCK min;
Vin = VREF for DQ, DQS and DM
Active standby current:
CS  VIH min; CKE  VIH min; One Bank Active-Precharge;
tRC = tRAS max; tCK = tCK min;
DQ, DM and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock cycle
Operating current:
Burst = 2; Reads; Continuous burst; One Bank Active;
Address and control inputs changing once per clock cycle;
CL = 2; tCK = tCK min; IOUT = 0mA
Operating current:
Burst = 2; Write; Continuous burst; One Bank Active;
Address and control inputs changing once per clock cycle;
CL = 2; tCK = tCK min;
DQ, DM and DQS inputs changing twice per clock cycle
Auto Refresh current: tRC = tRFC min
Self Refresh current: CKE  0.2V; external clock on; tCK = tCK min
Random Read current: 4 Banks Active Read with activate every
20nS, Auto-Precharge Read every 20 nS;
Burst = 4; tRCD = 3; IOUT = 0mA;
DQ, DM and DQS inputs changing twice per clock cycle;
Address changing once per clock cycle
MAX.
UNIT NOTES
-4 -5/-5I/-5A
75
65
7
90
80
7, 9
5
5
25
20
7
25
20
20
20
20
20
mA
35
30
7
140
120
7, 9
135
115
7
70
65
7
2
2
210
175
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Publication Release Date: Aug. 27, 2013
Revision A03