W9425G6JH_13 Datasheet, PDF (26/52 Pages) Winbond – 4 M x 4 BANKS x 16 BITS DDR SDRAM

W9425G6JH
10.6 AC Characteristics and Operating Condition
SYM.
tRC
tRFC
tRAS
tRCD
tRAP
tCCD
tRP
tRRD
tWR
PARAMETER
Active to Ref/Active Command Period
Ref to Ref/Active Command Period
Active to Precharge Command Period
Active to Read/Write Command Delay Time
Active to Read with Auto-precharge Enable
Read/Write(a) to Read/Write(b) Command Period
Precharge to Active Command Period
Active(a) to Active(b) Command Period
Write Recovery Time
tDAL Auto-precharge Write Recovery + Precharge Time
tCK CLK Cycle Time
CL = 2
CL = 2.5
CL = 3
CL = 4
-4
MIN. MAX.
52
60
36 70000
16
16
1
16
8
15
(tWR/tCK)
+
(tRP/tCK)
-
-
-
-
4
10
4
10
-5/-5I/-5A
MIN. MAX.
55
70
40 100000
15
15
1
15
10
15
(tWR/tCK)
+
(tRP/tCK)
7.5
12
6
12
5
12
-
-
tAC _{Data Access Time from CLK, CLK}
-0.7
0.7
-0.7
0.7
tDQSCK
tDQSQ
tCH
tCL
tHP
tQH
tRPRE
tRPST
tDS
tDH
tDIPW
tDQSH
tDQSL
tDSS
tDSH
tWPRES
tWPRE
tWPST
tDQSS
tIS
tIH
tIS
tIH
tIPW
DQS Output Access Time from CLK, CLK
Data Strobe Edge to Output Data Edge Skew
CLk High Level Width
CLK Low Level Width
CLK Half Period (minimum of actual tCH, tCL)
DQ Output Data Hold Time from DQS
DQS Read Preamble Time
DQS Read Postamble Time
DQ and DM Setup Time to DQS, slew rate 0.5V/nS
DQ and DM Hold Time to DQS, slew rate 0.5V/nS
DQ and DM Input Pulse Width (for each input)
DQS Input High Pulse Width
DQS Input Low Pulse Width
DQS Falling Edge to CLK Setup Time
DQS Falling Edge Hold Time from CLK
Clock to DQS Write Preamble Set-up Time
DQS Write Preamble Time
DQS Write Postamble Time
Write Command to First DQS Latching Transition
Input Setup Time (fast slew rate)
Input Hold Time (fast slew rate)
Input Setup Time (slow slew rate)
Input Hold Time (slow slew rate)
Control & Address Input Pulse Width (for each input)
-0.6
0.45
0.45
min
(tCL,tCH)
tHP-0.5
0.9
0.4
0.4
0.4
1.75
0.35
0.35
0.2
0.2
0
0.25
0.4
0.85
0.6
0.6
0.7
0.7
2.2
0.6
0.4
0.55
0.55
1.1
0.6
0.6
1.15
-0.6
0.45
0.45
Min,
(tCL,tCH)
tHP-0.5
0.9
0.4
0.4
0.4
1.75
0.35
0.35
0.2
0.2
0
0.25
0.4
0.72
0.6
0.6
0.7
0.7
2.2
0.6
0.4
0.55
0.55
1.1
0.6
0.6
1.25
tHZ _{Data-out High-impedance Time from CLK, CLK}
0.7
0.7
tLZ
tT(SS)
tWTR
tXSNR
tXSRD
tREFI
tMRD
Data-out Low-impedance Time from CLK, CLK
SSTL Input Transition
Internal Write to Read Command Delay
Exit Self Refresh to non-Read Command
Exit Self Refresh to Read Command
Refresh Interval Time (8K/ 64mS)
Mode Register Set Cycle Time
-0.7
0.7
-0.7
0.7
0.5
1.5
0.5
1.5
2
2
72
75
200
200
7.8
7.8
8
10
UNIT NOTES
nS
tCK
nS
tCK
18
nS
16
16
tCK
11
nS
tCK
11
nS
tCK
11
nS
tCK
11
19, 21-23
19, 21-23
20-23
20-23
nS
tCK
nS
tCK
µS
17
nS
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Publication Release Date: Aug. 27, 2013
Revision A03