W9425G6JH_13 Datasheet, PDF (3/52 Pages) Winbond – 4 M x 4 BANKS x 16 BITS DDR SDRAM

W9425G6JH
12.10 Auto-precharge Timing (Write Cycle) ...............................................................................................42
12.11 Read Interrupted by Read (CL = 2, BL = 2, 4, 8)..............................................................................43
12.12 Burst Read Stop (BL = 8) .................................................................................................................43
12.13 Read Interrupted by Write & BST (BL = 8) .......................................................................................44
12.14 Read Interrupted by Precharge (BL = 8) ..........................................................................................44
12.15 Write Interrupted by Write (BL = 2, 4, 8)...........................................................................................45
12.16 Write Interrupted by Read (CL = 2, BL = 8) ......................................................................................45
12.17 Write Interrupted by Read (CL = 3, BL = 4) ......................................................................................46
12.18 Write Interrupted by Precharge (BL = 8)...........................................................................................46
12.19 2 Bank Interleave Read Operation (CL = 2, BL = 2).........................................................................47
12.20 2 Bank Interleave Read Operation (CL = 2, BL = 4).........................................................................47
12.21 4 Bank Interleave Read Operation (CL = 2, BL = 2).........................................................................48
12.22 4 Bank Interleave Read Operation (CL = 2, BL = 4).........................................................................48
12.23 Auto Refresh Cycle ..........................................................................................................................49
12.24 Precharged/Active Power Down Mode Entry and Exit Timing ..........................................................49
12.25 Input Clock Frequency Change during Precharge Power Down Mode Timing.................................49
12.26 Self Refresh Entry and Exit Timing...................................................................................................50
13. PACKAGE SPECIFICATION .......................................................................................................................51
14. REVISION HISTORY ...................................................................................................................................52
Publication Release Date: Aug. 27, 2013
-3-
Revision A03