W9425G6JH_13 Datasheet, PDF (33/52 Pages) Winbond – 4 M x 4 BANKS x 16 BITS DDR SDRAM

W9425G6JH
f. Verified under typical conditions for qualification purposes.
g. TSOP II package devices only.
h. Only intended for operation up to 266 Mbps per pin.
i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below
0.5 V/nS as shown in Table 2. The Input slew rate is based on the lesser of the slew rates
determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.
j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew
rates differ, as shown in Tables 3 & 4. Input slew rate is based on the larger of AC-AC delta rise,
fall rate and DC-DC delta rise, fall rate. Input slew rate is based on the lesser of the slew rates
determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.
The delta rise/fall rate is calculated as:
{1/(Slew Rate1)}-{1/(slew Rate2)}
For example: If Slew Rate 1 is 0.5 V/nS and Slew Rate 2 is 0.4 V/nS, then the delta rise, fall rate is
-0.5 nS/V. Using the table given, this would result in the need for an increase in tDS and tDH of 100
pS.
k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/nS. The
I/O slew rate is based on the lesser of the AC-AC slew rate and the DC-DC slew rate. The input
slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC)
to VIL(DC), and similarly for rising transitions.
m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve
setup and hold times. Signal transitions through the DC region must be monotonic.
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Publication Release Date: Aug. 27, 2013
Revision A03