W9425G6JH_13 Datasheet, PDF (44/52 Pages) Winbond – 4 M x 4 BANKS x 16 BITS DDR SDRAM

W9425G6JH
12.13 Read Interrupted by Write & BST (BL = 8)
CLK
CLK
CAS Latency = 2
CMD READ
BST
WRIT
DQS
DQ
Q0 Q1 Q2 Q3 Q4 Q5
D0 D1 D2 D3 D4 D5 D6 D7
Burst Read cycle must be terminated by BST Command to avoid I/O conflict.
12.14 Read Interrupted by Precharge (BL = 8)
CLK
CLK
CMD
READ
PRE
CAS Latency = 2
DQS
DQ
CAS Latency
Q0 Q1 Q2 Q3 Q4 Q5
CAS Latency = 3
DQS
DQ
CAS Latency
Q0 Q1 Q2 Q3 Q4 Q5
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Publication Release Date: Aug. 27, 2013
Revision A03