W9425G6JH_13 Datasheet, PDF (38/52 Pages) Winbond – 4 M x 4 BANKS x 16 BITS DDR SDRAM

W9425G6JH
12.6 Mode Register Set (MRS) Timing
CLK
CLK
CMD
MRS
tMRD
NEXT CMD
ADD
Register Set data
A0
A1
Burst Length
A2
A3
Addressing Mode
A4
A5
CAS Latency
A6
A7 "0"
Reserved
A8
DLL Reset
A9 "0"
A10 "0"
A11 "0"
Reserved
A12 "0"
BA0 "0"
BA1 "0"
Mode Register Set
or
Extended Mode
Register Set
* "Reserved" should stay "0" during MRS cycle.
A2
A1
A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
A3
0
1
A6
A5
A4
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
A8
0
1
BA1
BA0
0
0
0
1
1
0
1
1
Burst Length
Sequential
Interleaved
Reserved
Reserved
2
2
4
4
8
8
Reserved
Reserved
Addressing Mode
Sequential
Interleaved
CAS Latency
Reserved
2
3
4
Reserved
2.5
Reserved
DLL Reset
No
Yes
MRS or EMRS
Regular MRS cycle
Extended MRS cycle
Reserved
- 38 -
Publication Release Date: Aug. 27, 2013
Revision A03