W91031 Datasheet, PDF (3/29 Pages) Winbond – LOW POWER CMOS INTERGRATED CIRCUIT

Preliminary W91031
PIN CONFIGURATION
INP
1
INN
2
GCFB
3
VREF
4
TEST1
5
RNGDI
6
RNGRC
7
W91031
Top View
RNGON
8
MODE
9
OSCI
10
OSCO
11
VSS
12
24
VDD
23
ALGRC
22
ALGR
21
ALGO
20
INTN
19
FCDN
18
FDRN
17
DATA
16
DCLK
15
FSKE
14
SLEEP/RESET
13
TEST2
PIN DESCRIPTION
PIN NAME TYPE
DESCRIPTION
1
INP
I Non-inverting Input of the gain control op-amp.
2
INN
I Inverting Input of the gain control op-amp.
3 GCFB
O Op-amp Feed-back Gain Control signal. Select the input gain by
connecting this pin and the INN pin with a feed-back resistor. It is
recommended that the op-amp be set to unity gain.
4 VREF
O Reference Voltage. Nominally, VDD/2 is used to bias the input of the gain
control op-amp.
5 TEST1
I Test pin, Must be connected to VDD for normal operation.
6 RNGDI
I Ring Detect Input (Schmitt trigger input). Used for ring detection and line
reversal detection. Must maintain a voltage between VDD and VSS.
7 RNGRC
O Ring RC (Open drain output and schmitt trigger input). Used to set the
time interval from the end of RNGDI pin to the inactive condition of the
RNGON pin. An external resistor must connected to VDD and a capacitor
connected to VSS, the time interval is the RC time constant.
8 RNGON
O Ring detection output (Low active). Indicates the detection of line reversal
and/or ringing.
9 MODE
I FSK Data interface MODE select. Sets the FSK data output interface in
mode 0 when low, or in mode 1 when high.
10 OSCI
I Oscillator Input. A 3.579545 MHz crystal or ceramic resonator should be
connected between this pin and the OSCO pin. May be driven by an
external clock source.
Publication Release Date: August 2000
-3-
Revision A1