W91031 Datasheet, PDF (18/29 Pages) Winbond – LOW POWER CMOS INTERGRATED CIRCUIT

Preliminary W91031
FSK Detection, continued
PARAMETER
SYMBOL CONDITION MIN. TYP.* MAX. UNITS NOTES
Input FSK to FCDN High Delay
tCA
FCDN
8
mS
Hysteresis
8
mS
Note: " * " typical figure are at VDD = 5V and temperature = 25° C are design aids only, not guaranteed and not subject to
production testing.
3-Wire Interface (Mode 0)
PARAMETER
SYMBOL CONDITION MIN. TYP.* MAX. UNITS NOTES
Rise Time
tRR
200
nS
4
Fall Time
tRF
FDRN
200
nS
4
Low Time
tRL
415
416
417
µS
2
Rate
DATA
1188 1200 1212 bpS
1
Input FSK to Data Delay
tIDD
1
5
mS
Rise Time
tR
200
nS
4
Fall Time
tF
DCLK
200
nS
4
DATA to DCLK Delay
tDCD
DATA
6
416
µS
1, 2, 3
DCLK to DATA Delay
tCDD
6
416
µS
1, 2, 3
Frequency
fDCLK0
1201.6 1202.8 1204
Hz
2
High Time
tCH
DCLK
415
416
417
µS
2
Low Time
tCL
415
416
417
µS
2
DCLK to FDRN Delay
tCRD DCLK, FDRN 415
416
417
µS
2
Notes:
" * " Ttypical figure are for VDD = 5V and temperature = 25° C, are design aids only, not guaranteed and not subject to production
testing.
1: FSK input data rate at 1200 +/-12 baud.
2: OSCI frequency at 3.579545 MHz +/-0.1%.
3: Function of signal condition.
4: 50 pF loading.
3-Wire Interface (Mode 1)
PARAMETER
SYMBOL CONDITION MIN. TYP.* MAX. UNITS NOTES
Frequency
fDCLK1
1
MHz
Duty Cycle
DCLK
30
70
%
Rise Time
tR1
20
nS
DCLK Low Set-up to FDRN
tDDS
DCLK,
500
nS
DCLK Low Hold Time After
tDDH
FDRN
500
nS
FDRN
Note: " * " typical figure are at VDD = 5V and temperature = 25° C are design aids only, not guaranteed and not subject to
production testing.
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