W91031 Datasheet, PDF(21/29 Page) Winbond – LOW POWER CMOS INTERGRATED CIRCUIT

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W91031 Datasheet, PDF (21/29 Pages) Winbond – LOW POWER CMOS INTERGRATED CIRCUIT

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Preliminary W91031

DCLK

VHM

VLM

t R1

VHM = 0.7 VDD , VLM = 0.3 VDD

Figure 8-7. DCLK Mode 1 Input Timing

Nth byte data

(N + 1)th byte data

Demodulated

stop start

internal

b6 b7

0 b0 b1 b2 b3 b4 b5 b6 b7

0 b0

bit stream

t RL

FDRN

DCLK

Note 1

t DDS

t DDH

Note 2

1/f DCLK1

DATA

b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7

(N - 1)th byte data

Nth byte data

Notes:

1. FDRN cleared to high by DCLK.

2. FDRN not cleared, low for maximum time (1/2 bit width).

Figure 8-8. Serial Data Interface Timing of FSK Demodulation in Mode 1

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Publication Release Date: August 2000

Revision A1

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