W91031 Datasheet, PDF (23/29 Pages) Winbond – LOW POWER CMOS INTERGRATED CIRCUIT

Preliminary W91031
Tip/A
V DD
22nF
430K
34K
W91031
V DD
V DD
V _DD
0.1uF
Ring/B
0.33uF
V DD
22nF
430K
34K
464K
53K6 60K4
0.1 uF
V _DD
0.1uF
V_DD
V _DD
INP
INN
GCFB
VREF
TEST1
RNGDI
RNGRC
RNGON
VDD
ALGRC
ALGR
ALGO
INTN
FCDN
FDRN
DATA
R1 R2
200K
150K
MODE
OSCI
DCLK
FSKE
12K
+
0.01uF
0.22uF
OSCO
SLEEP/
RESET
Vz
VSS
TEST2
Must reset by
-
470K
microcontroller
or by RC pulse.
Resistor must have 1% tolerance.
Resistor may have 5% tolerance.
Crystal is 3.579545MHz with 0.1% frequency tolerance.
R1, R2 must calculated according to the formula of Figure 7-6(a)
for Bellcore or BT application.
FSK 3-wire interface Mode 0 selected.
Figure 9-2. Application Circuit with Improved Common Mode Noise Immunity
Application Environment
There are three major timing differences for caller ID sequences, Bellcore, BT and CCA. Figure 9-3 is
the timing diagram for the Bellcore on-hook data transmission and Figure 9-4 is the timing diagram
for the Bellcore off-hook data transmission. Figure 9-5 is the timing diagram for the BT caller display
service on-hook data transmission and Figure 9-6 is the timing diagram for the BT caller display
service off-hook data transmission. Figure 9-7 is the timing diagram for the CCA caller display service
for on-hook data transmission.
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Publication Release Date: August 2000
Revision A1