W91031 Datasheet, PDF (20/29 Pages) Winbond – LOW POWER CMOS INTERGRATED CIRCUIT

Preliminary W91031
DATA
tR
t DCD
DCLK
t CL
VHM = 0.7 VDD , VCT = 0.5 VDD , VLM = 0.3 VDD
t CDD
tF
tR
tF
t CH
VHM
VCT
VLM
VHM
VCT
VLM
Figure 8-4. Data and DCLK Mode 0 Ouput Timing
t RF
t RR
VHM
FDRN
VCT
VLM
t RL
VHM = 0.7 VDD , VCT = 0.5 VDD , VLM = 0.3 VDD
Figure 8-5. FDRN Output Timing
Tip/Ring
DATA
1st byte data
start
stop
start
2nd byte data
stop
start
1* 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1* 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1 0 b0
t IDD
start
1st byte data
b0 b1 b2 b3 b4 b5 b6 b7
stop
start
2nd byte data
stop
start
b0 b1 b2 b3 b4 b5 b6 b7
DCLK
FDRN
1/fDCLK0
t CRD
t RL
* Mark bit or redundant stop bit(s), will be omitted.
Figure 8-6. Serial Data Interface Timing of FSK Demodulation in Mode 0
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