W91031 Datasheet, PDF (28/29 Pages) Winbond – LOW POWER CMOS INTERGRATED CIRCUIT

Preliminary W91031
A/B Wires
RNGON
SLEEP
INTN
TE DC load
TE AC load
FSKE
FCDN
FDRN
DCLK
DATA
Line Reversal
Ring Burst
A
B
Ch. Seizure Mark
Message
C
D
E
F
First Ring Cycle
...
250 - 400 mS
Note 2
Note 1
...
50 - 150 mS
Note 4
Note 3
...
...
...101010...
Data
A = 200 - 450 mS
B >= 500 mS
C = 80 - 262 mS
D = 45 - 262 mS
E <= 2.5 sec (500 mS typical)
F >= 200 mS
Figure 9-7. Input and Output Timing of CCA Caller Display Service Data Transmission
Notes:
1. The CPE designer may choose to set FSKE always high while the the CPE is on-hook and the FSK signal is expected.
2. TW/P & E/312 specifies that the AC and DC loads should be applied between 250−400 mS after the end of the ring burst.
3. TW/P & E/312 specifies that the AC and DC loads should be removed between 50−150 mS after the end of the FSK signal.
The W91031 may also be placed in a sleep condition.
4. The W91031 may not be woken up at the first ring cycle after the FSK data had been processed.
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